Board Design Engineer

Join SpaceX as a Senior RFIC Design Engineer in our Silicon Engineering team. In this pivotal role, you will be responsible for designing innovative RF integrated circuits that drive our next-generation space technologies. Collaborate with a team of experts to push the boundaries of technology while ensuring the highest standards of quality and performance.

At SpaceX, we believe in a future where humanity explores the stars, and we are dedicated to developing the technologies to make that vision a reality. Our ultimate goal is to enable human life on Mars.RFIC DESIGN ENGINEER (SILICON ENGINEERING)As part of SpaceX, you will leverage our extensive experience in building rockets and spacecraft to support the deployment of Starlink, the world's most advanced broadband internet system. Starlink features the largest satellite constellation globally, providing fast and reliable internet to millions of users. We design, build, test, and operate all system components, including thousands of satellites and user-friendly consumer receivers that allow connectivity within minutes. Join us in maximizing Starlink's global impact for communities and businesses.We are seeking a highly motivated and proactive RF/Analog IC engineer to collaborate with world-class cross-disciplinary teams, including systems, firmware, architecture, design, validation, and product engineering. In this position, you will develop cutting-edge next-generation RFICs for deployment in both space and terrestrial infrastructures. These innovations will enable connectivity in previously unreachable, unaffordable, or unreliable areas. Help us deliver next-generation solutions to enhance the Starlink network's performance and capabilities.

Founded on the vision of making humanity a multi-planetary species, SpaceX is pioneering the technologies to enable human life on Mars. Our mission extends beyond the stars; we are also transforming global connectivity through Starlink, the most advanced broadband internet system in the world.SENIOR RTL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX, we leverage our extensive experience in rocket and spacecraft development to successfully deploy Starlink, the world's largest satellite constellation. This initiative is providing high-speed, reliable internet to millions across the globe. We design, build, test, and operate all components of the system, from thousands of satellites to consumer receivers that enable users to connect with ease, and the software that integrates it all. As we continue to expand Starlink's global reach, we seek exceptional engineers to enhance its utility for communities and businesses worldwide.We are in search of a proactive and intellectually curious Senior RTL Design Engineer to collaborate with our elite, cross-disciplinary teams, including systems, firmware, architecture, design, validation, product engineering, and ASIC implementation. In this role, you will be at the forefront of developing next-generation FPGAs and ASICs that will be deployed in both space and terrestrial infrastructures. Your contributions will facilitate connectivity in areas that have previously lacked affordable and reliable access, thereby enhancing the capabilities of the Starlink network.

As an RFIC Layout Designer at Space Exploration Technologies Corp., you will play a pivotal role in the design and development of cutting-edge radio frequency integrated circuits (RFICs). Our team is dedicated to pushing the boundaries of technology and innovation, and we are looking for a talented individual who shares our passion for excellence.Your responsibilities will include collaborating with cross-functional teams to create robust layout designs that meet stringent performance specifications. You will utilize advanced design tools and methodologies to ensure high-quality outputs while adhering to project timelines.

Join SpaceX as a Senior RFIC Layout Designer, where you'll contribute to cutting-edge technology in the aerospace industry. In this role, you will be responsible for designing and implementing RF Integrated Circuit (RFIC) layouts, collaborating with a talented team of engineers, and ensuring the highest standards of quality and performance.We are looking for passionate individuals who are eager to push the boundaries of technology and innovation. Your expertise in RFIC layout design will be instrumental in the success of our projects.

Join SpaceX as a Design Verification Engineer, where you'll play a critical role in the development of innovative ASICs for our advanced Starlink network. Collaborating with top-tier teams, you will be responsible for digital ASIC verification at both block and system levels. Your expertise in writing and reviewing test plans, developing test harnesses, and automating test case generation will significantly enhance our connectivity solutions. As part of our mission to expand reliable internet access globally, your contributions will help shape the future of space-based technology and connectivity.

At SpaceX, we’re on a mission to revolutionize space exploration and connectivity. As a Senior Design Verification Engineer in our Silicon Engineering team, you will play a pivotal role in developing state-of-the-art ASICs that facilitate unprecedented connectivity for our Starlink network. Collaborating with a diverse team of engineers across systems, firmware, architecture, and product engineering, you will ensure high-quality digital ASIC verification at both block and system levels. Your technical expertise will contribute to the design, testing, and validation of advanced technologies, enhancing the performance and reliability of our groundbreaking satellite internet system.

At SpaceX, our mission is to make humanity multi-planetary. We are pioneering the development of innovative technologies to facilitate human life on Mars and provide unparalleled broadband connectivity across the globe through Starlink, the largest satellite constellation in history. We are in search of a dedicated and skilled Principal Design Verification Engineer to join our Silicon Engineering team. In this pivotal role, you will collaborate with exceptional cross-disciplinary teams to design and validate next-generation ASICs that enhance connectivity in previously underserved areas. Your contributions will be crucial in maximizing the capabilities and performance of the Starlink network while delivering groundbreaking solutions that impact millions of users worldwide.

Cerebras Systems is at the forefront of AI technology, developing the world’s largest AI chip, which is 56 times larger than conventional GPUs. Our innovative wafer-scale architecture delivers AI compute power equivalent to dozens of GPUs, all integrated onto a single chip. This unparalleled design allows us to achieve industry-leading training and inference speeds, enabling machine learning practitioners to run extensive ML applications seamlessly without the complexities of managing multiple GPUs or TPUs.We proudly serve a diverse clientele, including leading model laboratories, global corporations, and pioneering AI startups. Notably, OpenAI has entered into a multi-year partnership with us to deploy 750 megawatts of our technology, revolutionizing key workloads with ultra-high-speed inference.Our wafer-scale architecture powers the fastest Generative AI inference solution available, boasting speeds over ten times faster than traditional GPU-based hyperscale cloud inference services. This significant increase in speed is set to enhance the user experience of AI applications, allowing for real-time adjustments and improved intelligence through advanced agentic computation.

At SpaceX, we believe in a future where humanity explores the stars. We are actively developing groundbreaking technologies to enable human life on Mars.SOC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)Join us in leveraging our extensive experience in rocket and spacecraft development to deploy Starlink, the world’s most advanced broadband internet system. As the largest satellite constellation, Starlink provides fast and reliable internet to millions globally. We design, build, test, and operate every aspect of the system, including thousands of satellites and consumer receivers that allow users to connect swiftly. We are looking for elite engineers to harness Starlink’s potential for communities and businesses worldwide.We are on the lookout for a motivated, proactive, and intellectually curious engineer to collaborate with our world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You will be developing next-generation ASICs for deployment in space and ground infrastructures across the globe. These chips will enhance connectivity in areas where it has not been available, affordable, or reliable. Your contributions will be pivotal in delivering innovative solutions that expand the capabilities of the Starlink network.

At SpaceX, we envision a future where humanity explores the cosmos, driven by innovation and groundbreaking technology. Our mission is to develop the capabilities necessary for establishing human life on Mars. Join us as we revolutionize the way the world connects.Senior ASIC Design Engineer - Silicon EngineeringAs a pivotal member of SpaceX, you will leverage our extensive expertise in aerospace engineering to enhance Starlink, the globe's most advanced broadband internet system. As the largest satellite constellation in existence, Starlink is delivering fast, reliable internet to millions worldwide. We are responsible for designing, building, testing, and operating every component of this system—from thousands of satellites to consumer receivers that enable instant connectivity. We are just beginning to explore Starlink's vast potential and are on the lookout for exceptional engineers to unlock its benefits for communities and businesses across the globe.We are in search of an enthusiastic, self-driven, and inquisitive engineer who will collaborate with world-class interdisciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop state-of-the-art next-generation FPGAs and ASICs for space and ground infrastructure deployment worldwide. Your contributions will enable connectivity in regions where it has previously been unavailable, unaffordable, or unreliable. Your work will help deliver cutting-edge solutions that will enhance the performance and capabilities of the Starlink network.

At SpaceX, we believe in a future where humanity explores the cosmos, and we are dedicated to making that a reality. Our innovative technologies aim to enable human life on Mars and beyond.LEAD ASIC DESIGN ENGINEER - SILICON ENGINEERINGSpaceX is at the forefront of revolutionizing global communications with Starlink, the most advanced broadband internet system in existence. As part of the world’s largest satellite constellation, Starlink delivers fast and reliable internet to millions and is set to expand its impact further. We design, build, test, and operate every component of this groundbreaking system, from thousands of satellites to user-friendly consumer receivers and integrated software solutions. Join us in harnessing the full potential of Starlink to benefit communities and businesses worldwide.We are looking for a proactive and intellectually curious Lead ASIC Design Engineer to collaborate with exceptional cross-functional teams, including systems, firmware, architecture, design, validation, product engineering, and ASIC implementation. In this role, you will create state-of-the-art, next-generation FPGAs and ASICs to support operations in space and ground infrastructures globally. Your contributions will enhance connectivity in previously underserved areas, delivering innovative solutions that will elevate the performance and capabilities of the Starlink network.

Join SpaceX as a Senior ASIC/SOC Verification Engineer in Sunnyvale, CA, where you will play a vital role in the development of cutting-edge ASICs for space and ground applications. Collaborate with cross-functional teams to create innovative solutions that enhance the Starlink network's capabilities and connectivity. Your expertise in digital ASIC verification will drive the execution of complex designs, ensuring reliability and performance in unprecedented environments.

At SpaceX, we believe that a future where humanity explores the stars is immensely more thrilling than one where we remain Earth-bound. Our mission is to develop cutting-edge technologies that will make this vision a reality, with the ultimate goal of facilitating human life on Mars.Lead Principal DFT Engineer - Silicon EngineeringWe are looking for an enthusiastic and innovative engineer to join our elite team at SpaceX, where we leverage our expertise in rocket and spacecraft development to enhance Starlink – the most advanced broadband internet system in the world. Starlink is the largest satellite constellation ever built, delivering fast and reliable internet connectivity to millions of users globally. Our team designs, builds, tests, and operates every aspect of this groundbreaking system, from thousands of satellites to user-friendly consumer receivers and the integrated software that powers it all.As a Lead Principal DFT Engineer, you will collaborate with a diverse group of experts across multiple disciplines, including systems, firmware, architecture, design, validation, product engineering, and ASIC implementation. In this pivotal role, you will be responsible for developing next-generation ASICs that will be deployed both in space and on the ground, expanding connectivity to previously unreachable locations. Your contributions will be vital in advancing the performance and functionalities of the Starlink network.

Join intuitive as a Senior Mechanical Design Engineer and leverage your expertise in mechanical engineering to drive innovative design solutions. You will be at the forefront of developing cutting-edge mechanical systems, working collaboratively with cross-functional teams to ensure product excellence. Your role will encompass the entire design process, from concept to prototype, ensuring designs meet performance, manufacturability, and cost objectives.

About Applied IntuitionApplied Intuition, Inc. is at the forefront of the physical AI revolution. Established in 2017 and currently valued at $15 billion, this Silicon Valley powerhouse is developing the essential digital infrastructure required to infuse intelligence into every moving machine worldwide. Our solutions cater to diverse sectors including automotive, defense, trucking, construction, mining, and agriculture, focusing on three main pillars: tools and infrastructure, operating systems, and autonomy. Trusted by eighteen of the top twenty global automakers, as well as the United States military and its allies, Applied Intuition is dedicated to delivering physical intelligence. Our headquarters is based in Sunnyvale, California, and we have additional offices located in Washington, D.C.; San Diego; Ft. Walton Beach, Florida; Ann Arbor, Michigan; London; Stuttgart; Munich; Stockholm; Bangalore; Seoul; and Tokyo. Discover more at applied.co.We are committed to an in-office culture and expect our employees to work primarily from their Applied Intuition office five days a week. However, we understand the value of flexibility and trust our employees to manage their schedules responsibly. This may include occasional remote work, starting the day with morning meetings from home, or leaving early to attend to family obligations.About the RoleWe are seeking a Senior Engineer to take ownership of our HD maps, overseeing the entire process from start to finish. Our product suite utilizes HD maps to meet our clients' diverse needs across multiple applications, including localized information calculations, data queries across extensive maps, and map visualization and inspection. In this role, you will have the unique opportunity to shape the future of our mapping solutions by collaborating closely with fellow engineers and our customers.At Applied Intuition, You Will:Lead the implementation of HD maps and manage associated feature areas across all our products.Define our map storage format to accommodate additional features and enhance the distribution of map data, emphasizing user interfaces, data pipelines, and SDKs.

Cerebras Systems is a pioneer in AI technology, renowned for creating the world’s largest AI chip, which is an astounding 56 times larger than traditional GPUs. Our innovative wafer-scale architecture provides unparalleled AI computing capabilities equivalent to dozens of GPUs on a single chip, while ensuring the programming simplicity of a single device. This unique approach enables Cerebras to achieve unmatched training and inference speeds, allowing machine learning practitioners to seamlessly execute large-scale ML applications without the complexity of managing vast arrays of GPUs or TPUs. Cerebras' impressive clientele includes leading model laboratories, global enterprises, and cutting-edge AI-focused startups. Recently, OpenAI announced a multi-year partnership with Cerebras, enhancing transformative workloads through ultra-high-speed inference utilizing 750 megawatts of scale. With our groundbreaking wafer-scale architecture, Cerebras Inference delivers the fastest Generative AI inference solution globally, achieving speeds over 10 times faster than GPU-based hyperscale cloud inference services. This significant speed enhancement is revolutionizing the user experience in AI applications, enabling real-time iterations and boosting intelligence through advanced computational capabilities.About The RoleAs the Lead RTL Design Engineer, you will play a pivotal role in our exceptional team responsible for designing and developing the next iterations of the Cerebras Wafer Scale Engine (WSE). This position demands extensive expertise in RTL design and integration, with a strong emphasis on delivering high-performance, power-efficient, and scalable solutions. Additionally, you will oversee collaboration with external ASIC vendors and work closely with design verification, physical design, software, and system teams to translate innovative semiconductor architectures from concept to production, addressing the unique challenges associated with building WSE systems.

About the TeamFounded within X, Google's Moonshot Factory, Taara is dedicated to ensuring that billions of individuals have access to reliable and affordable internet. We are at the forefront of high-throughput, long-range free-space optical communication (FSOC), utilizing eye-safe lasers to transmit high-speed data wirelessly between terminals. Join us in revolutionizing wireless communication and bridging the digital divide.About the RoleWe are in search of a Senior Photonic Packaging Design Engineer to spearhead the development of next-generation photonic integrated modules within our R&D team. This role is essential in creating advanced wireless optical communication systems grounded in integrated optical phased arrays.The ideal candidate will be responsible for the design and execution of micro-optic assemblies involving silicon photonics and III-V dies, collaborating with outsourced semiconductor assembly and test (OSAT) vendors. This position demands extensive expertise in modeling, optimization, assembly, and testing of photonic packaging. A successful candidate will have significant experience in micro-lens-based packaging design, thermal management of III-V materials, thermo-optical package modeling, and optimizing silicon photonic coupling for manufacturability and reliability.We seek a driven individual who thrives in a dynamic environment and is passionate about tackling complex challenges that can lead to significant technological advancements.How You Will Make an Impact:Lead the development of innovative photonic packaging solutions that prioritize manufacturability and reliability.Play a key role in system-level optimization and product strategy formulation.Exhibit a strong commitment to utilizing technology to improve lives and a desire to contribute to this mission.Qualifications:Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, Applied Physics, or a related discipline.Minimum of five years of industry experience with proven success in photonic packaging design.Deep knowledge of micro-lens design for III-V and silicon photonic packaging.Proficiency in thermo-mechanical package modeling and thermal management of III-V components.Experience in optimizing packaging for manufacturability and reliability considerations.

Join Intuitive Surgical, a pioneering company in robotic-assisted surgery, as a Senior Mechanical Design Engineer. In this role, you will be instrumental in designing and developing innovative mechanical systems that enhance surgical procedures. You will work collaboratively with cross-functional teams to ensure that our products meet the highest standards of quality and performance.