Role SummaryAs a Principal Engineer in Systems Design Engineering, you will take full ownership of the end-to-end PCIe system design for our NVMe SSD product line. This encompasses client laptops and enterprise servers, guiding the process from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and establishing firmware design guidelines that ensure robust link training, link transitions, and low-power behavior. This pivotal role sits at the intersection of PCIe specification compliance, NVMe operational behavior, firmware architecture, platform interoperability, and power/performance optimization.Key Responsibilities· Lead the architecture of system-level PCIe Gen5/Gen6 from an NVMe SSD endpoint perspective.· Define and oversee PCIe + NVMe integration across various SSD products.· Conduct PHY + MAC IP reviews, establishing integration requirements and constraints.· Manage SoC/ASIC integration, including clocks, resets, power domains, straps, lane mapping, and sidebands.· Develop PCIe SFR + firmware guidelines covering flow control, LTSSM observability, power states, and error handling.· Oversee link and low power transitions, including DLRM, L1, L1SS, L0p, ASPM, clock-down, and APST coordination.· Facilitate bring-up and debugging processes: enumeration, speed negotiation, width detection, stability, and AER/error recovery.· Tune customer requirements focusing on latency/power, performance, reliability, and consistency.· Provide expert knowledge regarding PCIe configuration and extended capability registers.· Act as the technical authority for cross-team and customer escalations.Detailed Responsibilities (End-to-End PCIe for NVMe SSD)1. PHY/MAC IP Review (System Design Perspective)· Understand criteria for PHY/MAC/controller IP, including Gen5/Gen6 readiness and equalization capability.· Review IP documents for compliance features and link speed support.· Specify platform-facing requirements such as retimer/redriver compatibility.2. ASIC/SoC Integration Ownership· Integrate PCIe subsystems focusing on clock handling, reset behavior, and power domains.· Define lane policies for NVMe, including width detection and recovery strategies.
Feb 24, 2026