IP Software Generalist

About Etched Etched builds the first AI inference system tailored for transformers, delivering more than 10 times the performance of a B200 while cutting costs and latency. The company’s ASIC technology supports products that outpace traditional GPUs, making real-time video generation and advanced reasoning possible. Backed by hundreds of millions in funding…

About Etched Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries. Role Overview The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack. What You Will Do Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems. Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning. Debug complex datapath and protocol issues in RTL and testbench environments. Work directly with architects and designers to validate functionality and design intent. Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging. Help build reusable DV infrastructure, coverage models, and improve verification methodologies. Qualifications Expert knowledge of UVM and SystemVerilog. Strong analytical and debugging skills for complex digital designs. Solid understanding of computer architecture and core digital design concepts. Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics. Preferred Additional background with verification tools and methodologies is beneficial.

wehrtyou is hiring a Design Verification Engineer to help ensure the quality and reliability of new designs. This position is available in Austin, Boulder, Chicago, London, or New York. Role overview This role centers on verifying the functionality of complex hardware or system designs. The Design Verification Engineer works closely with colleagues from different teams to review requirements, identify potential issues, and confirm that products meet high quality standards. What you will do Develop and maintain verification plans for new and existing designs Create and execute test cases to validate product functionality Collaborate with engineering and product teams to address issues and improve processes Location Positions are available in Austin, TX; Boulder, CO; Chicago, IL; London, UK; and New York, NY.

Join Interface as a Founding Sales Development Representative! We seek a driven, competitive individual who is passionate about achieving success. Our fast-paced environment is built on hard work and the ability to create a pipeline from the ground up. If you thrive on challenge, love to experiment, and are not afraid to reach out to prospects, we want to hear from you! Who You Are:You make quick, informed decisions that can pivot as needed.You proactively identify and address issues before they become problems.You are comfortable engaging with technical, industrial, and enterprise-level buyers.You have experience selling to or prospecting real companies with significant purchasing power.You excel in chaotic and ambiguous environments.What You'll Do:Engage directly with prospects to discuss their workflows, challenges, and buying triggers.Manage outbound prospecting through cold emails, LinkedIn, and phone calls.Research and penetrate multi-billion dollar industrial and energy companies.Qualify inbound and outbound leads to book high-quality meetings.Refine our messaging based on real conversations, not just theory.Act quickly—perfectionism can hinder progress.Real Talk:You’ll work with a hands-on GTM manager who has successfully led high-performing SDR teams (120%+ average quota) and facilitated SDR promotions to AE within a year.Expect direct feedback, live deal exposure, and genuine coaching—performance metrics that matter, not just activity counts.This role is remote, allowing you to be closer to our customers.Additional Information:We're seeking candidates based in Texas, particularly in Austin or Houston.Competitive compensation, substantial equity, and the opportunity to influence early-stage team dynamics.

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems. The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology. Role overview The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes: Synthesis Placement Clock tree synthesis Detailed routing Optimization Physical signoff verification Locations This position is based in Austin, Texas or Fremont, California.

About OLIXAt OLIX, we are at the forefront of revolutionizing the semiconductor industry. As AI technology rapidly evolves, the demand for advanced infrastructure grows, creating significant opportunities for innovation. Traditional hardware designs are becoming obsolete, and OLIX is leading the charge with our groundbreaking Optical Tensor Processing Unit (OTPU) that delivers unmatched performance and energy efficiency. Join us in shaping the future of AI hardware.The RoleWe are on the lookout for exceptional Senior/Staff Digital Verification Engineers who possess extensive expertise in CMOS digital design and verification. In this role, you will be responsible for ensuring the functional accuracy of high-speed, real-time data processing silicon—from initial algorithm modeling to verified RTL, sign-off, and silicon bring-up.As part of a dynamic, multidisciplinary team, you will contribute to the creation of innovative OTPUs where the digital, optical, and mixed-signal domains converge. We seek candidates who are passionate about developing high-performance systems that power the next generation of AI technology.Key ResponsibilitiesLead the comprehensive verification of high-throughput digital pipelines that support multi-GSPS input rates and continuous streaming data paths.Design and implement robust verification environments using SystemVerilog/UVM, focusing on constrained-random testing, coverage closure, and regression automation.Establish and execute assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.Utilize formal verification methods (property checking, assertions, equivalence checking) to enhance simulation-based verification and expedite bug detection.Model and validate algorithms with MATLAB/Simulink or Python to ensure functional equivalence from algorithmic models to RTL and gate-level sign-off.Assist with FPGA prototyping and silicon bring-up by crafting targeted test cases, debugging strategies, and post-silicon validation plans.Collaborate effectively with digital design, optical hardware, mixed-signal, and software teams to guarantee seamless integration and performance.

Renesas Electronics Corporation seeks a Staff Design Verification Engineer based in Austin. This position helps maintain high standards during the design verification process, contributing to technology that appears in a wide range of electronic products. Role overview This role focuses on ensuring quality and reliability by verifying design implementations. The work directly impacts technology used in many electronic devices, supporting Renesas’s reputation for dependable products. Key responsibilities Contribute to the design verification process for electronic technologies Help uphold quality standards throughout verification stages Support the development of products used in diverse electronic applications Location This position is based in Austin.

Join our dynamic team at Renesas Electronics as a Senior Staff Design Verification Engineer. In this pivotal role, you will leverage your expertise in design verification to ensure the highest quality of our semiconductor products. You will be responsible for developing and implementing verification strategies, collaborating with cross-functional teams, and driving innovation in our design processes.

At Tenstorrent, we are at the forefront of AI technology, transforming performance benchmarks, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. With a passionate team of technologists, we have engineered a high-performance RISC-V CPU from the ground up, driven by our enthusiasm for AI and our commitment to creating the premier AI platform. We prioritize collaboration, curiosity, and a relentless pursuit of challenging problems. Join us as we expand our team and welcome contributors of all experience levels.We are currently on the lookout for a SoC Physical Design Verification Engineer who will take charge of full-chip signoff and guarantee the manufacturability and high quality of silicon across advanced technology nodes. In this role, you'll spearhead physical verification closures (DRC, LVS, ERC, etc.), troubleshoot issues using standard industry PV tools, and work alongside RTL, PD, CAD, and packaging teams to ensure successful tapeouts. If you thrive in a dynamic environment and relish tackling intricate challenges in cutting-edge silicon, we want to hear from you.This position is hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.We invite applicants of various experience levels for this role. During the interview process, we will assess candidates for the appropriate level, and offers will be made accordingly, which may differ from the one in this posting.

Join Tenstorrent as a Full-Chip Physical Design Verification Engineer, where you will play a pivotal role in ensuring the integrity and performance of our cutting-edge semiconductor designs. You will collaborate closely with cross-functional teams to validate full-chip designs, enhancing their functionality, reliability, and efficiency.Your expertise will be crucial in developing and executing verification plans, identifying and resolving issues, and contributing to the advancement of our innovative technology. If you are driven by a passion for excellence and are eager to work in a dynamic environment, we want to hear from you!

At TerraFirma, we are revolutionizing the earth-moving industry for construction. Established by visionary former SpaceX engineers and supported by Bain Capital Ventures, TerraFirma is committed to automating construction processes, making them faster, more cost-effective, and safer.Our Vision & PurposeHaving been part of the teams at SpaceX that constructed the largest rocket in history and launched an unprecedented number of satellites, we learned that robust infrastructure is the backbone of progress. During our efforts at Starbase, we recognized that the most significant hurdle to launching missions to Mars was not merely the rocket construction but rather the slow and costly establishment of the necessary infrastructure. This included critical elements like buildings, roads, water supply, power systems, communication networks, and waste management, all of which consumed more time and resources than anticipated.This realization led us to understand that the engineering principles which enabled breakthroughs in space exploration and mass manufacturing could similarly transform infrastructure development. By applying simplification, iteration, acceleration, and automation to construction, we can usher in a new era of building practices.Accelerating infrastructure development not only paves the way for progress but also creates a sustainable model for addressing some of humanity's greatest challenges. The innovations we develop on Earth will set the stage for the technologies necessary for future settlement on Mars.Position OverviewAs a UI/UX Designer at TerraFirma, you will collaborate across the entire technology stack to create intuitive, high-performance interfaces for the real-time remote management of heavy machinery through innovative user interfaces. This role demands exceptional frontend skills to deliver seamless user experiences and backend proficiency to maintain a secure, scalable system architecture. Responsibilities will include prototyping data-rich visualizations, constructing pipelines for intricate sensor data (such as LiDAR, geospatial, and 3D data), and optimizing user interactions. You will engage in rapid prototyping and iterative testing with users. Additionally, you will assist in managing production environments, deploying applications, and adhering to best practices in networking, security, and deployment.Key ResponsibilitiesDesign and develop user-friendly, high-performance interfaces for task management, supervision, and the remote control of autonomous robots and workflows.Create real-time visualizations for complex data sets to enhance decision-making processes.

About Neuralink:At Neuralink, we are pioneering the development of advanced devices that facilitate a bi-directional interface with the human brain. Our innovative technology aims to restore movement to those with paralysis, enhance vision for the visually impaired, and transform the way humans engage with their digital environments.Team Overview:The Mechanical Engineering Team for Brain Interfaces is at the forefront of designing, constructing, and testing mechanical systems that are integral to our implants and chargers. Our team also focuses on developing testing infrastructure to expedite hardware development and manufacturing, designing electronic packaging for chargers and implant components, and crafting tooling for seamless integration with surgical robots.Role Overview and Responsibilities:As a Mechanical Engineering Intern, you will play a key role in the design and fabrication of hardware solutions for our cutting-edge brain-computer interface systems. This includes components for surgical robotics, automation, microfabrication, and more. You will engage in diverse projects from conception to production, leveraging your mechanical engineering expertise in this dynamic field. Your key responsibilities will include:Designing, constructing, testing, and validating systems for the implant and associated hardware components.Enhancing manufacturing processes and equipment to bolster in-house production capabilities.Scoping, designing, and iterating custom tooling and fixtures necessary for the implant assembly process.Collaborating with Quality Assurance, Electrical Engineering, BCI Software, Microfabrication, and Surgical Engineering teams to define system requirements and verification/validation testing protocols.Meeting aggressive project timelines to ensure prompt delivery from initial concept to final implementation.

Join Renesas Electronics Corporation as a Technical IP Management Specialist, where you will play a pivotal role in overseeing and managing our intellectual property portfolio. You will collaborate with cross-functional teams to ensure effective IP strategies that align with our corporate objectives and enhance our competitive edge in the marketplace.

At Tenstorrent, we are at the forefront of pioneering AI technology, dramatically transforming performance, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions evolve to integrate advancements in software models, compilers, platforms, networking, and semiconductors. Our talented team has meticulously crafted a high-performance RISC-V CPU from the ground up, united by a shared passion for AI and an unwavering commitment to creating the ultimate AI platform. We foster a culture of collaboration, curiosity, and a determination to tackle challenging problems. We are expanding our team and invite contributors across all experience levels to join us.We are on the lookout for a skilled Field Application Engineer to advocate for our groundbreaking RISC-V CPU and AI accelerator IP products globally. You will be responsible for managing comprehensive technical engagements, translating intricate architectural advantages into customer successes, and influencing our product roadmap through direct market insights. If you possess profound technical knowledge complemented by exceptional customer engagement abilities and are eager to promote the adoption of next-generation compute IP, we want you on our team.This position is hybrid, based out of the United States or Canada, located near one of our primary office locations.We welcome candidates of all experience levels for this role. During the interview process, assessment will determine the appropriate level, and offers will be aligned accordingly, which may differ from the level stated in this posting.

Join Renesas Electronics as a Senior Firmware Verification Engineer in Austin, Texas! In this pivotal role, you will be responsible for ensuring the quality and functionality of firmware products through rigorous testing and verification processes. You will collaborate with cross-functional teams to identify issues, develop test plans, and implement automation strategies to enhance product performance.

About Neuralink:At Neuralink, we are pioneering the development of innovative devices that facilitate a bi-directional interface with the human brain. Our mission is to restore movement to those affected by paralysis, enable sight for the visually impaired, and transform the way individuals engage with their digital environments.Team Overview:The Brain Interfaces Hardware Department is at the forefront of delivering cutting-edge chip architecture and silicon implementation for neural recording and stimulation system-on-chip (SoC) solutions, aimed at high-bandwidth brain-machine interface applications. Our team consists of highly skilled engineers dedicated to expanding the boundaries of current technology and shaping the future.Role & Responsibilities:As a Digital IC Design Engineer, you will be tasked with the micro-architecture design and register-transfer level (RTL) implementation of digital intellectual properties (IPs) and systems, focusing on high-throughput, low-power digital signal processors (DSPs) and general-purpose hardware accelerators. Ideal candidates will possess product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC.Micro-architecture design and RTL implementation of:Low-power digital signal processorsLow-power general-purpose hardware acceleratorsLow-power graphics processing unitsLow-power radio MAC/PHYLow-power serial link MAC/PHYCollaborate with firmware engineers to design and optimize hardware/software interfaces.Optimize application-specific architectures, including:Complex system modeling for energy and performance benchmarksWorkload analysis and modelingEnergy/performance profiling and analysisTrade-offs between architecture design, process technology, and workload typesBalancing cost and performance amidst manufacturing process variationsEngage in silicon bring-up tests with verification engineers.

Saronic Technologies is at the forefront of transforming maritime autonomy, committed to creating advanced solutions that significantly improve operational efficiency through innovative autonomous and intelligent platforms.Job OverviewWe are in search of a dedicated Systems Architecture, Integration, and Test Engineer (Test & Verification). In this crucial position, you will lead the verification, testing, and integration efforts for our state-of-the-art autonomous vessels. Your role will be essential in guaranteeing that our systems satisfy design specifications and performance standards through comprehensive verification and validation processes. You will design, plan, and implement testing campaigns at both subsystem and system levels, prioritizing reliability, safety, and integration efficacy. This entails defining test objectives and success metrics, equipping test articles, managing data collection and analysis, and conducting root cause investigations when discrepancies arise. You will collaborate closely with design engineers, test engineers, analysts, and operational teams to ensure that test outcomes inform design enhancements, thereby bolstering the reliability of each subsystem in our next-generation vessels. Your expertise will play a vital role in advancing the performance and dependability of our groundbreaking maritime technology as we forge ahead into the future of autonomous vessels.We understand that exceptional candidates may not always fulfill every requirement. We encourage individuals who are enthusiastic about our mission to apply, even if they do not meet all qualifications. Some of our most valued team members started their journeys this way. We appreciate innovators, problem-solvers, and quick learners, and we prioritize what you can contribute moving forward rather than solely your past experience. Your unique insights and experiences may be precisely what we need, so we welcome your application!ResponsibilitiesDevelop, own, and implement subsystem- and system-level verification and validation (V&V) plans to ensure designs meet functional, performance, autonomy, reliability, and safety requirements.Define test objectives, configurations, procedures, and success criteria for subsystem and full-system integration tests.Lead root cause analysis and failure investigations, implementing corrective actions for issues identified during R&D and qualification testing in collaboration with development, quality, and test teams.Analyze test results to uncover design flaws, system interactions, or performance gaps; effectively communicate findings and recommended actions.

Tenstorrent builds advanced AI hardware and software, with a focus on high-performance RISC-V CPUs. The team brings together specialists in software, compilers, platforms, networking, and semiconductors to tackle complex technical challenges. Collaboration and curiosity shape the company’s approach to product development. Role overview The Staff Engineer, CPU Core Verification leads verification at the CPU core level. This position plays a key part in defining the behavior of out-of-order RISC-V CPUs as they move from design to silicon. Location and work arrangement This is a hybrid role based in Austin, Texas. There is also an option to work from the Santa Clara, California office. Hiring process and leveling Tenstorrent reviews applicants with a range of backgrounds. During interviews, the team evaluates each candidate for the most suitable level. Final compensation aligns with the assessed level, which may differ from the one listed in this posting.

About Neuralink:At Neuralink, we are pioneering the development of advanced devices that create a seamless bi-directional interface with the human brain. Our groundbreaking technology aims to restore movement to individuals with paralysis, restore vision to the blind, and transform the way humans engage with the digital landscape.Team Overview:The Brain Interfaces Soc Department is at the forefront of chip architecture and silicon implementation for neural recording and stimulation systems-on-chip (SoC), tailored for high-bandwidth brain-machine interface applications. Our team consists of outstanding engineers dedicated to expanding the limits of current technology and shaping the future of neurotechnology.Role Overview & Responsibilities:As a Hardware and Software Co-Design Engineer, you will lead the design and implementation of micro-architecture and register-transfer level (RTL) digital IPs and systems, focusing on high-throughput, low-power digital signal processors (DSPs) and general-purpose hardware accelerators. You will play a crucial role in realizing cutting-edge brain-computer interfaces. We prefer candidates with a solid background in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC.Designing and implementing micro-architecture and RTL for:Low-power digital signal processorsGeneral-purpose hardware acceleratorsGraphics processing unitsRadio MAC/PHY interfacesSerial link MAC/PHY interfacesCollaborating with firmware engineers to optimize hardware/software interfacesConducting application-specific architecture optimization, including:Complex system modeling for energy and performance benchmarksWorkload analysis and modelingEnergy/performance profiling and analysisMaking architecture-level design trade-offs with process technology and workload typesBalancing cost and performance in the face of manufacturing process variationWorking closely with verification engineers on silicon bring-up tests