Qualifications:8 to 12 years of relevant experience in ASIC Verification Engineering.Proficient in System Verilog for both hardware design and verification.Extensive experience with Universal Verification Methodology (UVM) environments and methodologies.Strong programming skills in C and Python.Exceptional analytical and problem-solving abilities, capable of effectively addressing intricate technical challenges.
About the job
Join Our Innovative Team!
At High Tech Genesis, you'll have the opportunity to work with cutting-edge technology while collaborating with a passionate team dedicated to excellence. Become a part of a leading design services firm that is at the forefront of technological advancements.
Embark on Your Next Career Adventure!
Your key responsibilities will include:
Interpreting and comprehending architectural and functional requirements, engaging collaboratively with systems engineers and architects.
Conducting thorough validation of architectural functional blocks using diverse methodologies, including simulation, formal verification, and coverage techniques.
Creating detailed verification plans, including functional coverage and formal verification strategies.
Designing robust testbench environments and components, including agents, scoreboards, and test scenarios utilizing System Verilog UVM and/or C.
Executing coverage-driven verification, overseeing regression monitoring, and troubleshooting failures with the function's designer.
Providing consistent updates on verification progress.
About High Tech Genesis Inc.
High Tech Genesis Inc. is an Equal Opportunity Employer committed to fostering an inclusive work environment that values diverse perspectives and drives innovation. We are dedicated to supporting an accessible recruitment process and will provide accommodations upon request.
This job posting is no longer active and is not accepting applications.
Qualifications:8 to 12 years of relevant experience in ASIC Verification Engineering.Proficient in System Verilog for both hardware design and verification.Extensive experience with Universal Verification Methodology (UVM) environments and methodologies.Strong programming skills in C and Python.Exceptional analytical and problem-solving abilities, capable of effectively addressing intricate technical challenges.
About the job
Join Our Innovative Team!
At High Tech Genesis, you'll have the opportunity to work with cutting-edge technology while collaborating with a passionate team dedicated to excellence. Become a part of a leading design services firm that is at the forefront of technological advancements.
Embark on Your Next Career Adventure!
Your key responsibilities will include:
Interpreting and comprehending architectural and functional requirements, engaging collaboratively with systems engineers and architects.
Conducting thorough validation of architectural functional blocks using diverse methodologies, including simulation, formal verification, and coverage techniques.
Creating detailed verification plans, including functional coverage and formal verification strategies.
Designing robust testbench environments and components, including agents, scoreboards, and test scenarios utilizing System Verilog UVM and/or C.
Executing coverage-driven verification, overseeing regression monitoring, and troubleshooting failures with the function's designer.
Providing consistent updates on verification progress.
About High Tech Genesis Inc.
High Tech Genesis Inc. is an Equal Opportunity Employer committed to fostering an inclusive work environment that values diverse perspectives and drives innovation. We are dedicated to supporting an accessible recruitment process and will provide accommodations upon request.
