About the job
About Our Team:
At OpenAI, our Hardware organization is at the forefront of designing silicon and system-level solutions that cater to the specific needs of advanced AI workloads. Our team is dedicated to developing the next generation of AI-native silicon, collaborating closely with software and research partners to create hardware that seamlessly integrates with AI models. Beyond delivering production-grade silicon for OpenAI’s supercomputing infrastructure, we innovate with custom design tools and methodologies that are specifically optimized for AI.
About the Role:
We are on a mission to develop custom silicon that powers the next generation of cutting-edge AI models, and we are seeking seasoned Design Verification Engineers to ensure the functional integrity and robustness of our state-of-the-art ML accelerators. In this pivotal role, you will be responsible for verifying intricate hardware systems, spanning from individual IP blocks to complete SoC architectures. You will collaborate closely with architecture, RTL, software, and systems teams to ensure the delivery of reliable silicon at scale.
Key Responsibilities:
Lead the verification efforts for one or more components, including custom IP blocks, subsystems (such as compute, interconnect, and memory), or full-chip SoC functionality.
Develop comprehensive verification plans in alignment with architecture and microarchitecture specifications.
Create constrained-random, directed, and system-level testbenches utilizing SystemVerilog/UVM or equivalent methodologies.
Design and uphold stimulus generators, checkers, monitors, and scoreboards to guarantee optimal coverage and correctness.
Facilitate bug triage and root cause analysis, collaborating closely with design teams to drive resolutions.
Contribute to regression infrastructure, coverage analysis, and closure processes for both block-level and top-level environments.