About the job
Join Our Team at Etched
At Etched, we are pioneering the development of the first AI inference system specifically designed for transformers, achieving over 10x the performance and significantly lower costs and latency compared to traditional solutions like the B200. Our custom ASICs empower the creation of groundbreaking products, such as real-time video generation models and highly advanced reasoning agents. Backed by substantial investments from leading venture capitalists and a team of top engineers, we are reshaping the foundational technology of one of the fastest-growing industries in history.
Role Overview
We are looking for a talented Design Verification Engineer to become a vital part of our Systems/Performance Verification team. In this role, you will be responsible for ensuring that the custom IPs driving our innovative Sohu architecture—such as systolic arrays, DMA engines, and Network on Chip (NoC)—are reliable, high-performing, and ready for silicon implementation. This position requires innovative thinking, robust technical skills, and a passion for solving intricate verification challenges. You will collaborate closely with architects, RTL designers, and software/firmware/emulation teams to validate the accuracy and performance of our hardware-software integration.
Key Responsibilities
- Collaborate with architects and RTL designers to verify the performance features of the design and ensure alignment with performance models, both pre- and post-silicon.
- Partner with software and application developers to identify performance bottlenecks and optimize software solutions.
- Create comprehensive test plans and develop test infrastructure/tools aimed at performance tuning, correlation, and verification.
- Enhance and maintain architectural performance models.
- Design tests in SystemVerilog, Python, or other vectors to debug and correlate RTL with performance models.
- Develop SystemVerilog or Python-based checkers to validate performance features.
- Implement coverage monitors and perform coverage analysis to ensure comprehensive testing of all performance features.
- Investigate performance issues and execute performance tuning on silicon.
- Lead end-to-end performance tuning to guarantee optimal hardware utilization, software efficiency, and architectural coherence throughout the ASIC design lifecycle.