About the job
We are seeking a skilled Digital Verification Engineer with a strong foundation in Object-Oriented SystemVerilog principles, utilizing UVM/OVM/VMM methodologies. In this role, you will be responsible for verifying digital blocks, developing UVM-based testbenches, and crafting constraint-random test cases.
You will leverage your extensive hands-on experience to implement the UVM_REG API, and work with drivers, monitors, scoreboards, functional coverage, and assertions (SVA). Your expertise will also include debugging RTL and gate-level simulations to ensure high-quality verification for multiple tapeouts.

