About the job
Job Responsibilities:
Over 8 years of hands-on experience in Logic Verification.
Lead the development of comprehensive test plans and verification infrastructure for intricate IP/Sub-Systems or oversee significant deliverables for System-on-Chip (SoC).
Design and implement verification environments utilizing UVM methodology.
Develop reusable bus functional models, monitors, checkers, and scoreboards.
Drive functional coverage and ensure verification closure.
Collaborate effectively with architects, designers, and post-silicon teams.
Contribute hands-on to System Verilog Assertions (SVA) development through coding, porting, and maintaining.
Assist in the development of tools that support Design and Verification.
Debug failures and conduct root cause analysis in collaboration with various teams.