Manager, ASIC Design Engineering - Starshield Satellite Engineering

RESPONSIBILITIES:Lead a team dedicated to the digital design of ASICs and/or FPGAs for Starshield initiatives. Conduct architectural analyses for features, performance expectations, and system constraints. Develop specifications for subsystems and circuits, collaborating with modem/DSP and RFIC engineers to delineate hardware and software responsibilities. Define micro-architecture, implement RTL in Verilog/System Verilog, integrate into the top-level design, and deliver a fully verified, synthesis/timing clean design. Collaborate closely with the verification team to ensure comprehensive coverage and validation of the design. Engage with leaders from across the engineering organization to drive product requirements and push the performance boundaries for Starshield satellites. Recruit, train, develop, and retain exceptional team members who will excel in delivering solutions for our nation. Provide timing constraints for the IPs and assist the physical implementation team with synthesis, timing closure, and formal verification. Participate in silicon bring-up and validation, aiding in the development of automated test lab equipment for lab measurements. BASIC QUALIFICATIONS:Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related engineering discipline.5+ years of experience in RTL implementation and/or FPGA/ASIC development.2+ years of experience in a leadership role.