Mechanical Engineer - Facilities Design

Join our innovative team as an ASIC Physical Design Engineer in the vibrant city of Austin, Texas. In this role, you will leverage your expertise to design and implement cutting-edge ASIC physical layouts, ensuring high performance and reliability.As a key member of our engineering department, you'll collaborate with cross-functional teams to drive projects from conception through to completion, all while adhering to strict timelines and quality standards.

About Etched Etched builds the first AI inference system tailored for transformers, delivering over 10x higher performance with lower cost and latency than conventional approaches. The company’s ASIC technology powers advanced products, from real-time video generation to sophisticated reasoning agents. Backed by leading investors and staffed by top engineers, Etched is focused on reshaping the infrastructure that supports the fast-moving AI sector. Role Overview The Senior Physical Design Engineer will play a central role in block-level implementation and verification. This position focuses on driving timing closure and optimizing power, performance, and area (PPA). The engineer will oversee third-party design partners and help refine internal workflows to accelerate design cycles. What You Will Do Develop a deep understanding of physical design challenges and solutions Run physical design flows to achieve block closure, improve ASIC infrastructure, and automate design steps Work closely with RTL designers, offering feedback to improve PPA Create dashboards to monitor project convergence in physical design Refine tool flows and collaborate with EDA vendors to adopt new technologies Take responsibility for achieving block-level closure Manage relationships with third-party physical design service providers Who We’re Looking For 5 to 10+ years of hands-on experience in physical design Strong background in tools, flows, and methodologies from RTL synthesis through GDSII sign-off Proven track record in back-end design and timing closure on advanced nodes (5nm and below) Familiarity with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience using sign-off tools such as PrimeTime, Tempus, Voltus, and similar Knowledge of UPF-based low power design, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Creative thinker with strong problem-solving skills Location Austin

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems. The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology. Role overview The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes: Synthesis Placement Clock tree synthesis Detailed routing Optimization Physical signoff verification Locations This position is based in Austin, Texas or Fremont, California.

Join Atom Computing as a Principal ASIC Design Engineer, where you will play a pivotal role in the design and development of advanced ASICs for quantum computing applications. You will collaborate with a team of talented engineers and contribute to groundbreaking projects that push the boundaries of technology.

Wehrtyou is seeking a Physical Design Engineer to develop advanced physical layouts for semiconductor products. This role directly shapes hardware design and implementation, balancing high performance with manufacturability. Key responsibilities Create and refine physical layouts for semiconductor devices Collaborate with multidisciplinary teams to optimize designs Ensure layouts comply with industry standards for quality and reliability Support product delivery from initial concept through manufacturing Locations Austin, TX, United States Boulder, Colorado, United States Chicago, Illinois, United States London, United Kingdom New York, NY, United States Seattle, Washington, United States Work culture Engineers at Wehrtyou contribute to projects that help shape the future of technology. The team emphasizes collaboration, technical growth, and practical problem-solving.

At Tenstorrent, we are pioneering advancements in AI technology, setting new benchmarks for performance, usability, and cost-effectiveness. As AI transforms the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. Our talented team of technologists has built a high-performance RISC-V CPU from the ground up, driven by a shared enthusiasm for AI and a commitment to developing an exceptional AI platform. We prioritize collaboration, curiosity, and a dedication to tackling challenging problems. As we expand our team, we invite contributors of all experience levels to join us.We are looking for skilled Physical Design Engineers to develop high-performance blocks for our state-of-the-art CPU and AI/ML architectures. In this role, you'll manage the entire implementation process from synthesis to tapeout, collaborating with leading engineers to push the limits of performance, power, and area. If you are passionate about designing silicon that drives the future of AI computing and enjoy solving intricate design challenges, we would love to have you as part of our team.This position is hybrid, based in Austin, TX, Santa Clara, CA, or Fort Collins, CO.We welcome applicants with diverse experience levels. During the interview process, we will evaluate candidates to align offers with their respective skill levels, which may differ from the one stated in this posting.

Join Efficient Computer as a Lead RTL Design Engineer, where you will spearhead the development of cutting-edge RTL designs for our innovative hardware products. In this pivotal role, you will collaborate with a dynamic team to deliver high-performance solutions that meet the demands of our clients.

Join Tenstorrent as an AI/ML Physical Design Flow Engineer and contribute to our cutting-edge projects that leverage artificial intelligence and machine learning in physical design processes. You will work closely with a talented team to develop and optimize design flows, ensuring efficiency and high performance in our systems.

Join Stanley Consultants, an esteemed global consulting engineering firm recognized for its commitment to culture, ethics, and client satisfaction. We tackle complex challenges to foster a sustainable and interconnected world while adapting to technological advancements and resilient practices.With over a century of experience across energy, federal government, transportation, and water sectors, we are shaping the infrastructure that enhances lives. As an employee-owned organization, we prioritize a "People First" approach, valuing your voice, growth, and success.We provide flexible work arrangements, competitive compensation, comprehensive benefits, and the opportunity to build a fulfilling, long-term career.

At Tenstorrent, we are at the forefront of revolutionary AI technology, setting new benchmarks for performance, usability, and cost-effectiveness. As AI reshapes the computing landscape, our solutions adapt to integrate innovations across software models, compilers, platforms, networking, and semiconductors. Our talented team has engineered a high-performance RISC-V CPU from the ground up, driven by a passion for AI and a commitment to developing the premier AI platform. We foster a culture of collaboration, curiosity, and a relentless pursuit of solving complex challenges. We are expanding our team and are eager to welcome contributors of all experience levels.We are currently seeking a Senior Staff Physical Design Engineer specializing in EMIR to join our silicon team. In this pivotal role, you will spearhead electromigration (EM) and IR-drop simulations, ensuring resilient power delivery, signal integrity, and long-lasting reliability for high-performance integrated circuits (ICs). Collaborating closely with RTL, physical design, and analysis teams, you will execute power grid strategies that enhance performance, power efficiency, and area (PPA), especially at advanced nodes such as 7nm and below. Your expertise will also support EMIR sign-off and waiver methodologies across the chip hierarchy.This is a hybrid position based out of either Austin, TX or Santa Clara, CA.We encourage candidates from various experience backgrounds to apply. During the interview process, we will assess candidates for the appropriate level, and our offers will be aligned accordingly, which may differ from this posting.

At Tenstorrent, we are at the forefront of AI technology, transforming performance benchmarks, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. With a passionate team of technologists, we have engineered a high-performance RISC-V CPU from the ground up, driven by our enthusiasm for AI and our commitment to creating the premier AI platform. We prioritize collaboration, curiosity, and a relentless pursuit of challenging problems. Join us as we expand our team and welcome contributors of all experience levels.We are currently on the lookout for a SoC Physical Design Verification Engineer who will take charge of full-chip signoff and guarantee the manufacturability and high quality of silicon across advanced technology nodes. In this role, you'll spearhead physical verification closures (DRC, LVS, ERC, etc.), troubleshoot issues using standard industry PV tools, and work alongside RTL, PD, CAD, and packaging teams to ensure successful tapeouts. If you thrive in a dynamic environment and relish tackling intricate challenges in cutting-edge silicon, we want to hear from you.This position is hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.We invite applicants of various experience levels for this role. During the interview process, we will assess candidates for the appropriate level, and offers will be made accordingly, which may differ from the one in this posting.

At Tenstorrent, we are at the forefront of pioneering AI technology, setting new benchmarks for performance, usability, and cost-effectiveness. As AI reshapes the computing landscape, our solutions must adapt to integrate advances in software modeling, compilers, platforms, networking, and semiconductors. Our diverse group of technologists has successfully crafted a high-performance RISC-V CPU from the ground up, driven by a shared enthusiasm for AI and a relentless pursuit to create the finest AI platform. We cherish collaboration, curiosity, and a steadfast commitment to tackling complex challenges. As we expand our team, we invite contributors at all experience levels to join us.We are currently seeking a Timing Engineer to enhance our silicon team. In this pivotal role, you will spearhead static timing analysis and closure for intricate, high-performance designs. You will work in close partnership with logic, DFT, and physical design teams to troubleshoot constraints, optimize timing paths, and ensure our chips meet performance objectives across various corners and modes.This position is hybrid, based in Austin, TX, Fort Collins, CO, or Santa Clara, CA.We encourage candidates of all experience levels to apply. Throughout the interview process, candidates will be evaluated for their fit, and offers will correspond to the assessed level, which may differ from the one stated in this posting.

About Etched Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries. Role Overview The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack. What You Will Do Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems. Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning. Debug complex datapath and protocol issues in RTL and testbench environments. Work directly with architects and designers to validate functionality and design intent. Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging. Help build reusable DV infrastructure, coverage models, and improve verification methodologies. Qualifications Expert knowledge of UVM and SystemVerilog. Strong analytical and debugging skills for complex digital designs. Solid understanding of computer architecture and core digital design concepts. Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics. Preferred Additional background with verification tools and methodologies is beneficial.

At Tenstorrent, we are at the forefront of pioneering AI technology, challenging the norms of performance, usability, and cost-effectiveness. As AI reshapes the landscape of computing, we are committed to evolving our solutions to integrate advancements in software models, compilers, platforms, networking, and semiconductor technologies. Our dynamic team has successfully built a high-performance RISC-V CPU from the ground up, fueled by a collective passion for AI and a relentless drive to create the ultimate AI platform. We cherish collaboration, curiosity, and a strong commitment to tackling complex challenges. As we expand our team, we welcome contributors across all experience levels.We are currently on the lookout for a Physical Design Engineer to take charge of timing for subsystems within our AI accelerator chip. In this role, you will work closely with RTL designers during the design exploration phase to evaluate the feasibility and performance, power, and area (PPA) of micro-architectural features. Your tasks will involve developing timing constraints and guiding the transition to physical design implementation. Key responsibilities include synthesis, place and route, timing analysis and closure, and power optimization. With a wide design space available for AI accelerators, your contributions will be crucial in selecting micro-architecture design points that align with die-size and PPA objectives.This position offers a hybrid work environment, with options based in Austin, TX, Santa Clara, CA, or Fort Collins, CO.We invite candidates of all experience levels to apply. During the interview process, we will assess each candidate's fit for the appropriate level, and compensation will correspond accordingly, which may differ from the level indicated in this posting.

About Etched Etched builds the first AI inference system tailored for transformers, delivering more than 10 times the performance of a B200 while cutting costs and latency. The company’s ASIC technology supports products that outpace traditional GPUs, making real-time video generation and advanced reasoning possible. Backed by hundreds of millions in funding and a team of experienced engineers, Etched is reshaping the infrastructure behind today’s fastest-growing industry. Role Overview The Design Verification Engineer - Interface IP will join the Interface IP DV team in Austin. This position works closely with architects, designers, and external vendors to ensure architectural requirements are met when developing IP subsystems and interfaces. The role involves validating correctness and performance across the hardware-software stack, requiring technical skill, creativity, and persistence to solve complex verification problems. What You Will Do Own one or more IP subsystems, such as PCIe, Ethernet, CPU (ARC/ARM), low power peripherals, and sensors. Interpret vendor IP configurations and coordinate with the internal IP team. Build and maintain verification environments using UVM and SystemVerilog to check functional correctness, performance, and compliance with IP specifications. Work with integration and SoC DV teams to ensure external IPs interact smoothly within the overall chip design. Drive coverage closure and sign-off by setting metrics, spotting gaps, and verifying edge cases and stress scenarios thoroughly.

At Tenstorrent, we are at the forefront of pioneering AI technology, setting new standards for performance, user experience, and cost efficiency. As AI transforms the computing landscape, our solutions are evolving to integrate advanced software models, compilers, platforms, networking, and semiconductor innovations. Our dynamic team of technologists has engineered a high-performance RISC-V CPU from the ground up, driven by a shared enthusiasm for AI and a dedication to creating the best AI platform available. We prioritize teamwork, inquisitiveness, and a relentless pursuit of tackling challenging problems. We are expanding our team and are eager for contributors of all experience levels to join us.We are searching for an outstanding Senior SoC Physical Design Engineer to lead the top-level implementation of our intricate AI and CPU SoC designs. In this role, you will facilitate cross-disciplinary collaboration, crafting advanced floorplans, power grids, and clock networks, while ensuring design closure at the chip level. If you possess a talent for navigating the complexities of full-chip physical design and aspire to deliver next-generation AI hardware, your expertise is needed here.This position is hybrid, with work based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO.We encourage applications from candidates of varying experience levels. During the interview process, we will assess candidates for the appropriate seniority level, and compensation will reflect that level, which may differ from what is stated in this posting.

About OLIXAt OLIX, we are at the forefront of an AI revolution, tackling the unprecedented demand for faster and more efficient technology. Our OLIX Decode Accelerator 1 (DX-1) is pioneering a new paradigm in hardware design, specifically architected for decode. By integrating logic, data movement, packaging, optics, and interconnect on a rack-scale, we are setting new benchmarks for system-level performance, making it one of the most significant economic opportunities in the coming century.Role Overview:We are on the lookout for a talented Digital Design Manager to spearhead the development of digital subsystems for our next-gen high-speed mixed-signal ASICs. This hands-on leadership position emphasizes swift execution, precision delivery, and effective team management. You will guide your team in delivering sophisticated digital systems that incorporate high-bandwidth interfaces, deterministic control loops, and advanced mixed-signal blocks, ensuring projects are completed on time, within budget, and to the highest quality standards. As a key leader and technical expert, you will provide mentorship to engineers, uphold performance excellence, and ensure meticulous execution from concept to production.Key Responsibilities:Lead the comprehensive delivery of digital subsystems, ensuring deadlines are met without sacrificing quality.Establish and maintain robust design and verification processes to achieve first-silicon success.Mentor and develop a high-performing team of digital engineers, fostering a culture of accountability and continuous improvement.Ensure seamless collaboration with cross-functional teams, including analog, verification, layout, firmware, and testing to maintain project alignment.Define, communicate, and track project schedules, resource allocation, and risk management strategies.

Join our innovative team at Braze as a Lead Design Engineer, where you'll play a crucial role in shaping our product's design and functionality. Your expertise will guide the design process, ensuring that our solutions are not only functional but also aesthetically pleasing and user-friendly. You will collaborate with cross-functional teams, utilizing your technical skills to lead design projects from concept to completion.

Saronic Technologies is at the forefront of transforming maritime autonomy, committed to pioneering advanced solutions that enhance operational efficiency through cutting-edge autonomous platforms.Job Overview:We are looking for an exceptionally talented Physical Security Systems Engineer to oversee the design, implementation, integration, and lifecycle management of our enterprise physical security technologies. In this pivotal role, you will contribute to architectural and engineering initiatives encompassing video surveillance, access control, intrusion detection, perimeter security, and identity management, with a pronounced focus on cloud-based systems.Design and implement comprehensive enterprise physical security systems, including:Video Surveillance (IP-based camera systems)Access Control (cloud and on-premises)Intrusion Detection & Alarm SystemsLicense Plate Recognition (LPR)Intercom and Visitor Management SystemsResponsibilities:Architect and manage security system environments (cameras, access control, sensors, intercoms).Support integrations for:Single Sign-On (SSO)SCIM user provisioningRole-based access control (RBAC)Conditional Access policiesAssist in establishing standardized naming conventions, device deployment standards, and comprehensive system documentation.Ensure systems are scalable for multi-site/global deployments.Design secure Power over Ethernet (PoE) and network topology for cameras and controllers.Configure VLAN segmentation for security devices.Collaboration:Work closely with network engineers to:Implement Quality of Service (QoS) policiesEnsure proper bandwidth allocationMaintain secure firewall rules

Saronic Technologies stands at the forefront of innovation, steering the future of maritime operations with cutting-edge autonomous solutions that redefine efficiency and safety at sea.Job Overview: We are looking for a talented Physical Security Systems Engineer who will take charge of designing, implementing, integrating, and managing the lifecycle of our enterprise physical security technologies. This role involves collaborating on architectural and engineering projects encompassing video surveillance, access control, intrusion detection, perimeter security, and identity integrations, with a particular focus on cloud-managed systems and identity integration.