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Principal Engineer, Systems Design Engineering

SanDiskSeoul
On-site Full-time

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Experience Level

Mid to Senior

Qualifications

REQUIRED:Master's degree in Embedded Systems, VLSI, or Microelectronics, or a Bachelor's degree in Electronics & Communications, Electrical & Electronics, or Computer Science.8-14 years of experience in semiconductor product systems design or architecture. Proficient in C, C++/System C, Python, GIT, GitHub, and AGILE methodologies. Demonstrated ability to collaborate effectively within a global team across multiple geographies. Multi-disciplinary expertise, with familiarity in Firmware, Hardware, and ASIC design. PREFERRED:Knowledge of PCIe Gen5/6 technology. Hands-on experience with NVMe specifications. Previous involvement with storage systems, protocols, and NAND flash is a significant advantage. Exposure to storage systems, protocols, and DDR DRAM is also advantageous. Basic understanding of SSD system-level concepts.

About the job

As a Principal Engineer in Systems Design Engineering, you will take full ownership of the end-to-end PCIe system design for our NVMe SSD product line. This encompasses client laptops and enterprise servers, guiding the process from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and establishing firmware design guidelines that ensure robust link training, link transitions, and low-power behavior. This pivotal role sits at the intersection of PCIe specification compliance, NVMe operational behavior, firmware architecture, platform interoperability, and power/performance optimization.

Key Responsibilities

· Lead the architecture of system-level PCIe Gen5/Gen6 from an NVMe SSD endpoint perspective.

· Define and oversee PCIe + NVMe integration across various SSD products.

· Conduct PHY + MAC IP reviews, establishing integration requirements and constraints.

· Manage SoC/ASIC integration, including clocks, resets, power domains, straps, lane mapping, and sidebands.

· Develop PCIe SFR + firmware guidelines covering flow control, LTSSM observability, power states, and error handling.

· Oversee link and low power transitions, including DLRM, L1, L1SS, L0p, ASPM, clock-down, and APST coordination.

· Facilitate bring-up and debugging processes: enumeration, speed negotiation, width detection, stability, and AER/error recovery.

· Tune customer requirements focusing on latency/power, performance, reliability, and consistency.

· Provide expert knowledge regarding PCIe configuration and extended capability registers.

· Act as the technical authority for cross-team and customer escalations.

Detailed Responsibilities (End-to-End PCIe for NVMe SSD)

1. PHY/MAC IP Review (System Design Perspective)

· Understand criteria for PHY/MAC/controller IP, including Gen5/Gen6 readiness and equalization capability.

· Review IP documents for compliance features and link speed support.

· Specify platform-facing requirements such as retimer/redriver compatibility.

2. ASIC/SoC Integration Ownership

· Integrate PCIe subsystems focusing on clock handling, reset behavior, and power domains.

· Define lane policies for NVMe, including width detection and recovery strategies.

About SanDisk

SanDisk is a leader in the data storage industry, dedicated to innovating solutions that meet today's data demands and anticipating tomorrow's needs. With a legacy of groundbreaking advancements in flash and memory technologies, our products are integral to the digital landscape. We empower individuals and businesses to pursue their aspirations through our commitment to quality, innovation, and performance. As a recognized member of the World Economic Forum's Global Lighthouse Network, SanDisk showcases its manufacturing capabilities and sustainability achievements, driving forward the future of data technology.

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