About the job
Key Responsibilities
Establish, strategize, and execute comprehensive verification plans at both block and system levels.
Draft and assess test plans, while developing effective test harnesses and sequences.
Ensure the successful completion of the design verification process by achieving predefined metrics related to the test plan, functional coverage, and code coverage.
Engage closely with the Design team to troubleshoot, identify root causes, and rectify functional discrepancies within the design.
Work collaboratively with cross-functional teams, including Design, Modeling, Emulation, and Silicon Validation, to uphold the highest standards of design quality.
Essential Qualifications
Bachelor's degree in Electrical Engineering, Computer Science, or a related technical discipline.
Over 5 years of hands-on experience in block and system level verification employing SystemVerilog/UVM methodologies.
Demonstrated expertise with Electronic Design Automation (EDA) tools and proficiency in scripting languages such as Python, Perl, or Shell for verification tool development.
Experience in architecting and implementing Design Verification infrastructure, encompassing the entire verification cycle from planning to successful closure.
Desirable Qualifications
Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field.
Proficiency in creating UVM-based verification environments from the ground up.
Expertise in developing Python-based verification environments, including tools like cocotb.
Experience in IP or integration verification for high-speed interfaces such as PCIe, UCIe, UALink, and Ethernet.
Familiarity with verifying ARM/RISC-V-based sub-systems or SoCs.
Strong programming capabilities in Python.
Exceptional written and verbal communication skills.
Contact Information
For inquiries, please reach out via email: recruit@furiosa.ai
