About the job
Cerebras Systems is at the forefront of AI technology, creating the world’s largest AI chip, which is 56 times larger than traditional GPUs. Our unique wafer-scale architecture provides unparalleled AI compute power equivalent to dozens of GPUs on a single chip, coupled with the ease of programming as if it were a single device. This innovative design enables Cerebras to deliver unmatched training and inference speeds, allowing machine learning practitioners to seamlessly run extensive ML applications without the complexity of managing multiple GPUs or TPUs.
Cerebras' clientele consists of leading model labs, major corporations, and pioneering AI-native startups. Recently, OpenAI initiated a multi-year partnership with Cerebras, committing to deploying 750 megawatts of scale, revolutionizing critical workloads with ultra high-speed inference.
Our groundbreaking wafer-scale architecture enables Cerebras Inference to offer the fastest Generative AI inference solution globally, exceeding the speeds of GPU-based hyperscale cloud inference services by more than tenfold. This significant speed enhancement transforms the user experience in AI applications, facilitating real-time iterations and boosting intelligence through additional agentic computation.
About the Role
As a Senior IC Design Engineer specializing in IO Signal Integrity and Power Delivery, you will play a pivotal role in high-speed IO interface design and integration. Your expertise will drive both signal integrity (SI) and power delivery (PI) performance for our custom IP within the wafer-scale engine.
This position emphasizes thorough system analysis, architecture design, integration, and circuit design, spanning from the transistor level to external voltage regulators. You will ensure that both custom and third-party IP meet stringent performance, power, and reliability targets across die, 3D assembly, and system-level boundaries.
