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Senior IC Packaging Engineer at Axiado | San Jose

AxiadoSan Jose
On-site Full-time

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Experience Level

Senior

Qualifications

Qualifications:BSEE or MSEE (PhD preferred) in Electrical Engineering or a related field. At least 10 years of extensive experience in IC packaging for SoCs, ASICs, or memory products. In-depth hands-on expertise in Flip-Chip BGA (FCBGA), System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe). Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, advanced packaging materials, substrate technologies, and Design-for-Manufacturing (DFM) principles. Proven ability to work independently, make significant decisions, and execute effectively in a startup environment.

About the job

Axiado Corporation is on the lookout for a talented Senior IC Packaging Engineer to spearhead technical leadership and architectural ownership of cutting-edge IC and System-in-Package (SiP) solutions in a dynamic startup atmosphere. This position is tailored for an experienced technologist who merges extensive hands-on expertise with a comprehensive system-level perspective, thriving in ambiguous and impactful environments.

In this role, you will define and implement high-performance, low-power packaging architectures that encompass 2D and RDL-based fan-out (2.5D) and chiplet-based designs, driving efforts from initial technology exploration through to production ramp-up. Collaborating closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams, you will influence product execution and long-term packaging strategies.

Key Responsibilities

  • Act as the technical authority for IC and SiP packaging across various products and programs.
  • Own the package architecture and technology roadmap, ensuring alignment with product, cost, and scalability objectives.
  • Lead the development of chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
  • Guide hands-on package design and physical layout, focusing on critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and other multi-gigabit interfaces.
  • Define substrate stack-ups, materials, bump/RDL architectures, and Design-for-Manufacturing (DFM) guidelines for advanced nodes.
  • Drive signal integrity (SI), power integrity (PI), thermal, mechanical, and reliability trade-offs at the system and package levels.
  • Engage externally with OSATs, foundries, and key suppliers to facilitate technology development and manufacturing readiness.
  • Influence product roadmaps, risk management, and investment decisions through technical insights.
  • Establish scalable design methodologies, best practices, and reusable packaging flows.

About Axiado

Axiado is revolutionizing digital system control and management through its AI-enhanced security processors. Founded in 2017, Axiado has grown to over 100 employees and is committed to creating exceptional technology. We believe that talent combined with collaboration, respect, and a drive to innovate can change the world. If you share this passion and desire to disrupt the status quo, we encourage you to apply!

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