About the job
About Our Team
Founded at X, Google's Moonshot Factory, Taara is dedicated to connecting billions who currently lack access to affordable and high-speed internet. We are innovating in high-throughput, long-range free-space optical communication (FSOC) with our unique eye-safe laser technology that enables wireless transmission of data between two terminals. Join our mission to revolutionize wireless optical communication and help bridge the digital divide, paving the way for a brighter, more connected future.
About the Role
We are on the lookout for a Senior Photonic Design/Layout Engineer to be a pivotal part of our R&D team, focused on developing state-of-the-art photonic and electronic integrated modules for advanced wireless optical communication systems utilizing integrated optical phase arrays.
The ideal candidate will take ownership of the top-level layout and orchestrate the layout process for very-large-scale photonic integrated circuits (PICs) at Taara. This role involves collaborating with foundries and enhancing our photonic design as well as the software infrastructure for layout and verification. Extensive experience in photonic tape-outs, including overseeing tape-outs at commercial foundries, and in-depth knowledge of Python, Git, and gdsfactory are essential.
We seek a highly driven professional who excels in navigating ambiguity, thrives in a small, agile team environment, and is passionate about solving complex challenges that lead to significant technological progress.
Your Impact
Lead and deliver exceptional photonic integrated circuit layouts.
Contribute to photonic design, infrastructure, and vendor management.
Show a strong commitment to leveraging technology for positive global impact and a desire to be part of a team working towards this goal.
Qualifications
Ph. D. in Electrical Engineering, Applied Physics, Materials Science, or a related discipline.
A minimum of five (5) years of relevant industry experience showcasing significant contributions in photonic layout and design.
Hands-on experience with multiple tapeouts at commercial foundries across 45nm to 180nm nodes.
Proficient in top-level layout ownership, layout process management, and leading layout teams.
Deep expertise in Design Rule Checks (DRC) and Layout Versus Schematic (LVS) processes.
