About the job
About OLIX
At OLIX, we recognize that the demand for AI technology is accelerating at an unprecedented pace, leading to a significant infrastructure challenge. Current chip and power generation methods are insufficient to meet this demand. The industry is still reliant on outdated hardware designs, which are no longer effective. A transformative approach that enhances speed and efficiency represents the largest economic opportunity of the coming century. OLIX is pioneering this new paradigm with our Optical Tensor Processing Unit (OTPU), which delivers unmatched performance and energy efficiency that existing chips simply cannot achieve.
Your Role
We are in search of exceptional Senior/Staff Digital Design Engineers who specialize in CMOS digital design. You will take complete ownership of the design and implementation of high-speed, real-time data-processing silicon, from initial algorithm modeling through to verified RTL and silicon integration. Join a multidisciplinary team that is at the forefront of developing next-generation OTPUs, where digital, optical, and mixed-signal technologies converge. The ideal candidate will possess a robust background in electrical engineering and semiconductor physics, coupled with a fervor for creating reliable, high-performance digital circuits that propel AI hardware advancements.
Key Responsibilities
- Architect, design, and implement high-throughput digital pipelines (multi-GSPS input rates, continuous streaming data paths, deep pipelining, and hand-shaking) utilizing advanced CMOS nodes.
- Quickly prototype and iterate in FPGA (Xilinx/AMD, Intel, or equivalents): develop real-time demonstrations, validate high-speed transceivers, and integrate feedback into ASIC designs.
- Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence up to gate-level sign-off.
- Lead RTL development (SystemVerilog / Verilog / VHDL), encompassing synthesis, static-timing closure, and both formal and constrained-random verification.
- Evaluate power, performance, and area (PPA), employing innovative strategies to meet aggressive bandwidth-per-watt objectives.
- Collaborate with optical hardware, mixed-signal, and software teams to optimize data-converter interfaces, clock-domain crossings, and firmware abstractions.
- Mentor junior engineers, facilitate design reviews, and promote best-practice design methodologies.
Qualifications & Experience
- 7+ years of direct experience in digital design for high-performance applications.
- Strong proficiency in CMOS design methodologies and digital circuit development.
- Extensive experience with FPGA prototyping and algorithm validation.
- Expertise in RTL design languages (SystemVerilog / Verilog / VHDL) and verification processes.
- Familiarity with power, performance, and area trade-offs in digital design.
- Excellent collaborative and communication skills for cross-functional teamwork.
- Demonstrated ability to lead and mentor engineering teams.
