About the job
About OLIX
At OLIX, we are at the forefront of the AI revolution, addressing the critical infrastructure gap caused by the unprecedented demand for advanced technology. Our innovative approach transcends the limitations of decade-old hardware designs. We are pioneering the Optical Tensor Processing Unit (OTPU), a next-generation chip that delivers unparalleled performance and energy efficiency, setting the stage for transformative economic opportunities in the coming century.
The Role
We are on the lookout for exceptional Senior/Staff Digital Design Engineers with expertise in CMOS digital design, ready to take full ownership of the development of high-speed, real-time data-processing silicon. Your responsibilities will span from early algorithm modeling through to RTL verification and silicon bring-up. Join our multidisciplinary team to innovate at the intersection of digital, optical, and mixed-signal technologies. A solid foundation in electrical engineering and semiconductor physics, coupled with a passion for crafting high-performance digital circuits for cutting-edge AI hardware, is essential.
Responsibilities
Design and implement high-throughput digital pipelines capable of handling multi-GSPS input rates and continuous data streams using advanced CMOS technologies.
Rapidly prototype and iterate in FPGA environments (Xilinx/AMD, Intel, or similar) to create real-time demonstrations and optimize high-speed transceivers, incorporating feedback into ASIC development.
Model and validate algorithms using MATLAB/Simulink (or equivalent), ensuring functional equivalence up to gate-level sign-off.
Lead RTL development using SystemVerilog/Verilog/VHDL, focusing on synthesis, static-timing closure, and formal verification processes.
Conduct thorough analyses of power, performance, and area (PPA) metrics; implement innovative strategies to meet stringent bandwidth-per-watt targets.
Collaborate effectively with optical hardware, mixed-signal, and software teams to refine data converter interfaces, manage clock-domain crossings, and enhance firmware abstraction layers.
Mentor junior engineers, lead design reviews, and promote best practices in design methodologies.
Skills & Experience
A minimum of 7 years of hands-on experience in digital design for high-performance applications.
Proficient in RTL design and verification methodologies, with a strong grasp of digital design principles.
