Software Engineer, Drivers/Runtime (Windows)

Key ResponsibilitiesManage and operate the testing infrastructure for our software and hardware solutions.Conduct operations and maintenance on bare-metal equipment utilized for evaluations.Support the evaluation infrastructure to ensure successful product validation.

Join Furiosa AI as a Software Engineer focused on Developer Experience! In this role, you will collaborate with cross-functional teams to enhance the development workflow, tools, and processes that empower our engineering teams. Your contributions will be pivotal in creating efficient and high-quality software solutions that drive our mission forward.

Key ResponsibilitiesCraft and implement a robust end-to-end security architecture tailored for SoC-based products.Develop features for Secure Boot and Anti-rollback mechanisms.Manage Key Provisioning alongside Hardware Root of Trust.Oversee Secure Lifecycle State management (LCS) for firmware, keys, and devices.Design and integrate security modules to enhance firmware and system-level defenses.Conduct thorough vulnerability assessments, attack surface evaluations, and implement memory protection hardening strategies.Integrate, validate, and optimize hardware cryptographic engines including AES/GCM engines, TRNG, PKA, RSA, PQC, and hash accelerators.Establish secure firmware update and rollback protocols along with comprehensive product lifecycle controls.QualificationsDeep understanding of embedded security principles, including Secure Boot, key management, and cryptography.Demonstrated experience with TLS, X.509, ECC, AES, and various cryptographic or security libraries.Proficient in C/C++ or Rust for developing secure system software.Experience identifying and analyzing security vulnerabilities in SoC/FPGA-based systems.Practical experience with hardware cryptographic engines and security IP blocks (e.g., AES/GCM, SHA accelerators, TRNG/DRBG, PKA).Solid understanding of firmware and key lifecycle management.Preferred QualificationsFamiliarity with TPM, HSM, TrustZone, OP-TEE, or related hardware security architectures.Experience in implementing secure firmware signing, provisioning, and deployment pipelines.Background in validating cryptographic engines under standards such as FIPS 140-3, NIST CMVP.Security engineering experience specifically for AI accelerators, networking chips, or SoCs.Contribute to development practices aligned with standards such as FIPS, PSA Certified, CAVP, and CMVP.

Key ResponsibilitiesDesign, develop, and sustain Linux PCIe device drivers and kernel modules to optimize system performance.Enhance PCIe subsystem functionality, focusing on DMA, IOMMU, interrupts, and BAR mapping.Create user-space libraries and APIs that facilitate high-speed data transfers.Collaborate with hardware and firmware teams to construct comprehensive PCIe I/O pipelines.Devise effective memory management techniques and implement zero-copy data transfer mechanisms.

About the RoleWe are seeking a dedicated Security Engineer to report directly to the CTO. This role is instrumental in establishing the company's security framework and implementing a Zero Trust architecture across our organization.You will be responsible for developing security policies, configuring systems, managing accounts, controlling access, ensuring cloud security, and conducting penetration testing.Key ResponsibilitiesEstablish and execute an enterprise security strategy and policies based on Zero Trust principles.Build and operate identity and access management systems (SSO, IAM, RBAC, etc.).Design and configure security architecture for SaaS and cloud infrastructure (AWS, GCP, etc.).Diagnose and enhance security vulnerabilities within internal systems and services.Collaborate with development and infrastructure teams to integrate security practices (code reviews, CI/CD security, etc.).Set up and manage incident response systems and monitoring environments.

Key ResponsibilitiesDevise and execute comprehensive verification strategies for block/IP/SoC, establishing test benches to facilitate effective verification at various levels.Create and implement functional testing protocols based on the established verification test plans.Lead the design verification process to successful completion, adhering to defined metrics for functional and code coverage.Analyze, troubleshoot, and rectify functional discrepancies in the design, working closely with the design team.Engage in collaboration with cross-disciplinary teams, including Design, Modeling, Emulation, and Silicon Validation, to ensure superior design quality.

Key ResponsibilitiesDevelop and maintain test automation solutions to validate NPU hardware and associated software stacks.Enhance efficiency in large-scale evaluation tasks through the maintenance of automation scripts and frameworks.Design solutions for structuring, analyzing, and visualizing evaluation data.Support the operation of testing environments based on CI/CD methodologies.

Key ResponsibilitiesIntegrate and validate IP blocks within the System on Chip (SoC) architecture while assisting in the physical implementation process.Formulate specifications, architecture, and operational scenarios at the SoC level.Comprehend standard interface specifications (e.g., PCIe) and chip operational scenarios to effectively configure integrated IP blocks.Conduct performance analyses through chip-level simulations focusing on bus and memory bandwidth, alongside FPGA prototyping.

Key ResponsibilitiesDevelop and implement firmware solutions for Furiosa devices, ensuring optimal performance and reliability.Create and maintain device drivers tailored for Furiosa hardware, enhancing system integration.Establish testing frameworks to ensure the highest quality standards for firmware and device drivers.

Key ResponsibilitiesAssess the Power, Performance, and Area (PPA) metrics of our designs during the chip architecture planning phase.Conduct synthesis, perform logic equivalence checking, develop SDC and UPF, and execute static timing analysis.Collaborate effectively with design houses to ensure optimal project outcomes.

Join Our AI Transformation TeamOur dynamic AI Transformation Team is dedicated to tackling intricate engineering challenges through innovative machine learning techniques, transitioning these solutions into impactful real-world applications. We specialize in creating agent systems designed to automate problem-solving, constantly refining and enhancing our approaches.Our mission is to seamlessly connect research with practical application by constructing platforms that utilize agentic AI for tangible engineering solutions.Key ResponsibilitiesArchitect and develop the foundational infrastructure for our Agent System Framework.Implement essential components of the agent runtime, focusing on orchestration, context management, tool execution, and memory abstraction.Work alongside cross-functional teams to quickly prototype and scale new agent functionalities into production environments.Design and enhance developer-friendly interfaces including CLI tools and SDKs.Minimum QualificationsA Bachelor’s degree in Computer Science, a related technical discipline, or equivalent practical experienceProven experience in at least two of the following areas:Designing and managing distributed systems or extensive backend systems.Building and deploying machine learning/AI systems, particularly those based on LLMs, in a production setting.Developing agent systems, workflow engines, or orchestration frameworks.Backend development proficiency in Python, Go, or C++.Preferred QualificationsMaster’s or PhD degree in Engineering, Computer Science, or a related fieldDemonstrated success in designing and implementing agentic AI system frameworks in real-world or large-scale contexts.Hands-on experience in developing LLM-based applications (e.g., for tool utilization, planning, reasoning systems).Experience in creating developer tools, such as CLI or SDKs.Contact UsFor inquiries, reach out to us at: recruit@furiosa.ai

Key ResponsibilitiesDevelop and sustain ROM code along with software for early system initialization.Port and tailor Arm Trusted Firmware (TF-A / TF-M) to meet project needs.Implement essential system trust primitives including Secure Boot, firmware updates, and RoT components.Work closely with hardware teams for effective SoC bring-up, low-level debugging, and silicon validation.Design system-level software with a focus on performance, reliability, and security requirements.

About the RoleAt Furiosa AI, we are committed to enhancing the productivity of our compiler team by systematically designing and continuously improving our CI and development workflows.In this role, you will focus on transforming CI into a more reliable, efficient, and user-friendly system through the development of developer productivity tools, including CI orchestrators.Our compiler team executes large-scale tests across multiple clusters to optimize model performance in terms of both time and energy. Within this context, CI operates not merely as a pipeline executor but as a sophisticated orchestration system that coordinates complex workloads and resources, demanding high reliability and automated recovery capabilities.Aim for engineering that defines and resolves problems rather than simple operations.Engineers are encouraged to analyze issues independently and propose improvement directions.Important decisions are made collaboratively within the team.Improve both development productivity and stability through practical approaches.

ResponsibilitiesDevelop the PyTorch-Native Kernel Programming Model by designing an integration layer and runtime environments that facilitate the execution of custom kernels as native extensions in the PyTorch framework.Create a Tensor-Level Kernel Language by establishing high-level abstractions and programming models to support efficient model integration and expressive tensor operations.Implement a Virtual ISA to address performance bottlenecks through direct hardware control while preserving high-level programmability.Contribute to the Kernel Developer Ecosystem by building essential programming tools, technical specifications, and reference implementations to streamline kernel development and foster community contributions.

Join Furiosa AI as a Software Engineer specializing in Low Level Programming Interface & Runtime. In this role, you will develop and optimize low-level software systems that enhance the performance and efficiency of our cutting-edge AI technology.

Job ResponsibilitiesStay abreast of cutting-edge AI research trends, including LLM, Agentic AI, Diffusion, and Inference acceleration, and explore integration opportunities with our proprietary NPU.Lead groundbreaking AI research aimed at publication in top-tier academic conferences.Forge research collaborations with prestigious global institutions and manage associated projects.

Key ResponsibilitiesDesign and implement the NPU Management Interface (MI) firmware/software to facilitate seamless communication between Host/BMC and NPU devices.Develop and sustain MCTP, PLDM, and custom MI command handling for comprehensive out-of-band NPU management, monitoring, and control.Craft device-management features utilizing SMBus/I²C, I3C, PCIe VDM, or custom sideband channels.Integrate MI capabilities into the NPU firmware, including:Health and error reporting mechanismsThermal and power telemetry systemsRuntime status, utilization metrics, and intricate debug informationEnsure adherence to industry standards through thorough spec-driven design, implementation, and validation.Assist in bring-up processes, interoperability testing, rack-scale platform integration, and system-level validation.Formulate test strategies and validation tools aligned with MCTP and PLDM specifications.Conduct protocol compliance testing, regression testing, and interoperability verification.

Key ResponsibilitiesSpearhead the design of AI system PCBs.Create and refine schematics while providing layout consultation for PCBs.Analyze and offer insights on PCB signal integrity and power integrity.Essential QualificationsBachelor's degree in Electrical or Electronics Engineering.5 to 10 years of relevant industry experience.In-depth knowledge of passive components, DC-DC converters, LDOs, NOR-flash, DDR, and logic gates.Proficient in Allegro software for PCB design.Strong understanding of PCB stack-up configurations.Experienced in using measurement equipment effectively.Preferred QualificationsSolid understanding and hands-on experience with various VRM topologies.Comprehensive knowledge of passive components.Extensive experience in power supply system design.Experience with PCB-level power integration.Familiarity with circuit simulation tools such as SIMPLIS, Allegro, and HSPICE.Knowledge of high-speed circuit design principles.Contact Informationrecruit@furiosa.ai

Key ResponsibilitiesDesign and define architecture/microarchitecture specifications while taking full ownership of one or more chip modules, implementing them in RTL.Achieve convergence of functionality and Power, Performance, Area (PPA) within the design.Develop and refine designs in RTL (System Verilog or other HDLs), iterating to optimize power consumption, timing, and area efficiency.Construct straightforward test benches and troubleshoot intricate logic simulations.Minimum QualificationsA Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.A minimum of 2 years of relevant industry experience in chip design, particularly in RTL design (architecture and implementation), logic synthesis, verification, and timing closure.Proficient in implementing microprocessor simulators using C++ or other high-level programming languages.Experience in modeling the PPA of designs.Familiarity with scripting languages for automating simulation and analysis processes.Preferred QualificationsA Ph.D. in Electrical Engineering, Computer Science, or related field is advantageous.Experience in accelerator design is a plus.Knowledge of highly pipelined designs and multiple-clock-domain designs is preferred.Understanding of machine learning algorithms, compiler technologies, processor design, accelerators, and memory hierarchies.Familiarity with Chisel or RISC-V architectures is an advantage.Contact InformationFor inquiries, please reach out to: recruit@furiosa.ai