Staff Design Verification Engineer

wehrtyou is hiring a Design Verification Engineer to help ensure the quality and reliability of new designs. This position is available in Austin, Boulder, Chicago, London, or New York. Role overview This role centers on verifying the functionality of complex hardware or system designs. The Design Verification Engineer works closely with colleagues from different teams to review requirements, identify potential issues, and confirm that products meet high quality standards. What you will do Develop and maintain verification plans for new and existing designs Create and execute test cases to validate product functionality Collaborate with engineering and product teams to address issues and improve processes Location Positions are available in Austin, TX; Boulder, CO; Chicago, IL; London, UK; and New York, NY.

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems. The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology. Role overview The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes: Synthesis Placement Clock tree synthesis Detailed routing Optimization Physical signoff verification Locations This position is based in Austin, Texas or Fremont, California.

About OLIXAt OLIX, we are at the forefront of revolutionizing the semiconductor industry. As AI technology rapidly evolves, the demand for advanced infrastructure grows, creating significant opportunities for innovation. Traditional hardware designs are becoming obsolete, and OLIX is leading the charge with our groundbreaking Optical Tensor Processing Unit (OTPU) that delivers unmatched performance and energy efficiency. Join us in shaping the future of AI hardware.The RoleWe are on the lookout for exceptional Senior/Staff Digital Verification Engineers who possess extensive expertise in CMOS digital design and verification. In this role, you will be responsible for ensuring the functional accuracy of high-speed, real-time data processing silicon—from initial algorithm modeling to verified RTL, sign-off, and silicon bring-up.As part of a dynamic, multidisciplinary team, you will contribute to the creation of innovative OTPUs where the digital, optical, and mixed-signal domains converge. We seek candidates who are passionate about developing high-performance systems that power the next generation of AI technology.Key ResponsibilitiesLead the comprehensive verification of high-throughput digital pipelines that support multi-GSPS input rates and continuous streaming data paths.Design and implement robust verification environments using SystemVerilog/UVM, focusing on constrained-random testing, coverage closure, and regression automation.Establish and execute assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.Utilize formal verification methods (property checking, assertions, equivalence checking) to enhance simulation-based verification and expedite bug detection.Model and validate algorithms with MATLAB/Simulink or Python to ensure functional equivalence from algorithmic models to RTL and gate-level sign-off.Assist with FPGA prototyping and silicon bring-up by crafting targeted test cases, debugging strategies, and post-silicon validation plans.Collaborate effectively with digital design, optical hardware, mixed-signal, and software teams to guarantee seamless integration and performance.

About Etched Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries. Role Overview The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack. What You Will Do Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems. Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning. Debug complex datapath and protocol issues in RTL and testbench environments. Work directly with architects and designers to validate functionality and design intent. Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging. Help build reusable DV infrastructure, coverage models, and improve verification methodologies. Qualifications Expert knowledge of UVM and SystemVerilog. Strong analytical and debugging skills for complex digital designs. Solid understanding of computer architecture and core digital design concepts. Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics. Preferred Additional background with verification tools and methodologies is beneficial.

Join our dynamic team at Renesas Electronics as a Senior Staff Design Verification Engineer. In this pivotal role, you will leverage your expertise in design verification to ensure the highest quality of our semiconductor products. You will be responsible for developing and implementing verification strategies, collaborating with cross-functional teams, and driving innovation in our design processes.

At Tenstorrent, we are at the forefront of AI technology, transforming performance benchmarks, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. With a passionate team of technologists, we have engineered a high-performance RISC-V CPU from the ground up, driven by our enthusiasm for AI and our commitment to creating the premier AI platform. We prioritize collaboration, curiosity, and a relentless pursuit of challenging problems. Join us as we expand our team and welcome contributors of all experience levels.We are currently on the lookout for a SoC Physical Design Verification Engineer who will take charge of full-chip signoff and guarantee the manufacturability and high quality of silicon across advanced technology nodes. In this role, you'll spearhead physical verification closures (DRC, LVS, ERC, etc.), troubleshoot issues using standard industry PV tools, and work alongside RTL, PD, CAD, and packaging teams to ensure successful tapeouts. If you thrive in a dynamic environment and relish tackling intricate challenges in cutting-edge silicon, we want to hear from you.This position is hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.We invite applicants of various experience levels for this role. During the interview process, we will assess candidates for the appropriate level, and offers will be made accordingly, which may differ from the one in this posting.

About Etched Etched builds the first AI inference system tailored for transformers, delivering more than 10 times the performance of a B200 while cutting costs and latency. The company’s ASIC technology supports products that outpace traditional GPUs, making real-time video generation and advanced reasoning possible. Backed by hundreds of millions in funding and a team of experienced engineers, Etched is reshaping the infrastructure behind today’s fastest-growing industry. Role Overview The Design Verification Engineer - Interface IP will join the Interface IP DV team in Austin. This position works closely with architects, designers, and external vendors to ensure architectural requirements are met when developing IP subsystems and interfaces. The role involves validating correctness and performance across the hardware-software stack, requiring technical skill, creativity, and persistence to solve complex verification problems. What You Will Do Own one or more IP subsystems, such as PCIe, Ethernet, CPU (ARC/ARM), low power peripherals, and sensors. Interpret vendor IP configurations and coordinate with the internal IP team. Build and maintain verification environments using UVM and SystemVerilog to check functional correctness, performance, and compliance with IP specifications. Work with integration and SoC DV teams to ensure external IPs interact smoothly within the overall chip design. Drive coverage closure and sign-off by setting metrics, spotting gaps, and verifying edge cases and stress scenarios thoroughly.

Join Renesas Electronics as a Senior Firmware Verification Engineer in Austin, Texas! In this pivotal role, you will be responsible for ensuring the quality and functionality of firmware products through rigorous testing and verification processes. You will collaborate with cross-functional teams to identify issues, develop test plans, and implement automation strategies to enhance product performance.

Saronic Technologies is at the forefront of transforming maritime autonomy, committed to creating advanced solutions that significantly improve operational efficiency through innovative autonomous and intelligent platforms.Job OverviewWe are in search of a dedicated Systems Architecture, Integration, and Test Engineer (Test & Verification). In this crucial position, you will lead the verification, testing, and integration efforts for our state-of-the-art autonomous vessels. Your role will be essential in guaranteeing that our systems satisfy design specifications and performance standards through comprehensive verification and validation processes. You will design, plan, and implement testing campaigns at both subsystem and system levels, prioritizing reliability, safety, and integration efficacy. This entails defining test objectives and success metrics, equipping test articles, managing data collection and analysis, and conducting root cause investigations when discrepancies arise. You will collaborate closely with design engineers, test engineers, analysts, and operational teams to ensure that test outcomes inform design enhancements, thereby bolstering the reliability of each subsystem in our next-generation vessels. Your expertise will play a vital role in advancing the performance and dependability of our groundbreaking maritime technology as we forge ahead into the future of autonomous vessels.We understand that exceptional candidates may not always fulfill every requirement. We encourage individuals who are enthusiastic about our mission to apply, even if they do not meet all qualifications. Some of our most valued team members started their journeys this way. We appreciate innovators, problem-solvers, and quick learners, and we prioritize what you can contribute moving forward rather than solely your past experience. Your unique insights and experiences may be precisely what we need, so we welcome your application!ResponsibilitiesDevelop, own, and implement subsystem- and system-level verification and validation (V&V) plans to ensure designs meet functional, performance, autonomy, reliability, and safety requirements.Define test objectives, configurations, procedures, and success criteria for subsystem and full-system integration tests.Lead root cause analysis and failure investigations, implementing corrective actions for issues identified during R&D and qualification testing in collaboration with development, quality, and test teams.Analyze test results to uncover design flaws, system interactions, or performance gaps; effectively communicate findings and recommended actions.

Tenstorrent builds advanced AI hardware and software, with a focus on high-performance RISC-V CPUs. The team brings together specialists in software, compilers, platforms, networking, and semiconductors to tackle complex technical challenges. Collaboration and curiosity shape the company’s approach to product development. Role overview The Staff Engineer, CPU Core Verification leads verification at the CPU core level. This position plays a key part in defining the behavior of out-of-order RISC-V CPUs as they move from design to silicon. Location and work arrangement This is a hybrid role based in Austin, Texas. There is also an option to work from the Santa Clara, California office. Hiring process and leveling Tenstorrent reviews applicants with a range of backgrounds. During interviews, the team evaluates each candidate for the most suitable level. Final compensation aligns with the assessed level, which may differ from the one listed in this posting.

Join our dynamic Robotics Software Team at avride! We are seeking a skilled Verification & Test Engineer to assist in the development and testing of cutting-edge sensor and system software. This is a part-time, onsite position based at our Austin, TX office, requiring a commitment of 20 hours per week over a 6-month contract.

About OLIXAt OLIX, we are at the forefront of AI technology, revolutionizing the industry by addressing the significant infrastructure gap created by the rapid demand for advanced solutions. Our OLIX Decode Accelerator 1 (DX-1) is pioneering the future of chip design with its innovative architecture tailored specifically for decoding, enabling unprecedented performance through co-design principles.Role Overview:We are seeking a dynamic ASIC Digital Verification Manager to spearhead the functional verification of our next-generation high-speed mixed-signal ASICs. This is a pivotal leadership position focused on delivering results with agility, ensuring first-silicon success, managing talent, and fostering cross-functional collaboration. Your leadership will guide the verification of intricate digital systems incorporating high-bandwidth interfaces and advanced mixed-signal elements, all while adhering to timelines, budgets, and uncompromised quality standards.This is a unique opportunity to take charge of the verification process from architectural design through to mass production, holding substantial influence over strategic direction, talent management, and technical execution. If you excel in high-pressure environments where meticulous verification meets rapid execution, this role will place you at the core of groundbreaking ASIC development challenges.Key Responsibilities:Ownership of Execution & Speed – Direct the comprehensive verification of digital subsystems, encompassing testbench architecture, UVM development, functional and code coverage, formal verification, CDC/RDC sign-off, low-power verification, gate-level simulation, and FPGA prototyping, while ensuring adherence to aggressive timelines without sacrificing quality.Right-First-Time Delivery – Establish and enforce verification plans, sign-off criteria, and silicon correlation strategies that proactively identify issues pre-silicon, driving successful first-silicon outcomes.Team & Performance Management – Lead, mentor, and cultivate a high-performing, geographically dispersed team of engineers, emphasizing continuous growth and excellence in verification practices.

Join our innovative team at Braze as a Lead Design Engineer, where you'll play a crucial role in shaping our product's design and functionality. Your expertise will guide the design process, ensuring that our solutions are not only functional but also aesthetically pleasing and user-friendly. You will collaborate with cross-functional teams, utilizing your technical skills to lead design projects from concept to completion.

Join Efficient Computer as a Lead RTL Design Engineer, where you will spearhead the development of cutting-edge RTL designs for our innovative hardware products. In this pivotal role, you will collaborate with a dynamic team to deliver high-performance solutions that meet the demands of our clients.

Wehrtyou is seeking a Physical Design Engineer to develop advanced physical layouts for semiconductor products. This role directly shapes hardware design and implementation, balancing high performance with manufacturability. Key responsibilities Create and refine physical layouts for semiconductor devices Collaborate with multidisciplinary teams to optimize designs Ensure layouts comply with industry standards for quality and reliability Support product delivery from initial concept through manufacturing Locations Austin, TX, United States Boulder, Colorado, United States Chicago, Illinois, United States London, United Kingdom New York, NY, United States Seattle, Washington, United States Work culture Engineers at Wehrtyou contribute to projects that help shape the future of technology. The team emphasizes collaboration, technical growth, and practical problem-solving.

About Etched Etched builds the first AI inference system tailored for transformers, delivering over 10x higher performance with lower cost and latency than conventional approaches. The company’s ASIC technology powers advanced products, from real-time video generation to sophisticated reasoning agents. Backed by leading investors and staffed by top engineers, Etched is focused on reshaping the infrastructure that supports the fast-moving AI sector. Role Overview The Senior Physical Design Engineer will play a central role in block-level implementation and verification. This position focuses on driving timing closure and optimizing power, performance, and area (PPA). The engineer will oversee third-party design partners and help refine internal workflows to accelerate design cycles. What You Will Do Develop a deep understanding of physical design challenges and solutions Run physical design flows to achieve block closure, improve ASIC infrastructure, and automate design steps Work closely with RTL designers, offering feedback to improve PPA Create dashboards to monitor project convergence in physical design Refine tool flows and collaborate with EDA vendors to adopt new technologies Take responsibility for achieving block-level closure Manage relationships with third-party physical design service providers Who We’re Looking For 5 to 10+ years of hands-on experience in physical design Strong background in tools, flows, and methodologies from RTL synthesis through GDSII sign-off Proven track record in back-end design and timing closure on advanced nodes (5nm and below) Familiarity with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience using sign-off tools such as PrimeTime, Tempus, Voltus, and similar Knowledge of UPF-based low power design, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Creative thinker with strong problem-solving skills Location Austin

Saronic Technologies is at the forefront of transforming maritime autonomy, committed to crafting innovative solutions that elevate maritime operations through cutting-edge autonomous and intelligent platforms.Job OverviewWe are on the lookout for a skilled Composite Design Engineer to spearhead the structural design, analysis, and integration of composite materials into our advanced maritime platforms. You will play a crucial role in crafting lightweight, high-performance composite structures tailored for maritime environments while adhering to mission-critical DoD performance and survivability standards.Responsibilities Design, analyze, and optimize composite structures for autonomous maritime platforms, including hulls, decks, and enclosures.Develop 3D CAD models and 2D manufacturing drawings utilizing tools such as SolidWorks, Siemens NX, and Fibersim.Conduct hand calculations for the design and sizing of laminates using CLT tools.Collaborate closely with naval architects, mechanical engineers, and autonomy teams to seamlessly integrate composite structures with vessel systems.Establish material specifications and liaise with suppliers to procure suitable composite materials, including NCFs, resin systems, adhesives, and core materials.Create manufacturing plans and work in conjunction with both in-house and external fabricators to facilitate prototype and production builds.Ensure adherence to MIL-STD and DoD structural integrity, weight, and signature management requirements.Promote design-for-manufacturing (DFM) and design-for-assembly (DFA) principles.Assist in testing, validation, and qualification of composite assemblies in both laboratory and marine environments.Qualifications A Bachelor's degree or higher in Mechanical Engineering, Aerospace Engineering, Naval Architecture, or a related discipline.A minimum of 2 years of experience in composite structural design within aerospace, marine, automotive, or defense sectors.Robust knowledge of composite materials (such as carbon fiber, fiberglass, and resin infusion) and their layup techniques.Proficiency in CAD and FEA software (e.g., Femap (preferred), ANSYS, Abaqus).Familiarity with mechanical testing, structural validation, and failure analysis of composite systems.

About Neuralink:At Neuralink, we are pioneering technology that establishes a bi-directional interface with the human brain. Our innovative devices aim to restore movement to those who are paralyzed, restore sight to the visually impaired, and transform the way humans engage with their digital environments.Team Overview:The EPC team plays a crucial role in all engineering, procurement, and construction activities, from developing new greenfield sites to enhancing existing facilities. We collaborate with cross-functional teams to identify and address their present and future requirements, creating tailored environments that foster the growth of our research and engineering initiatives.We seek dynamic individuals who thrive in fast-paced settings, advocate for teamwork and transparent communication, and possess a genuine enthusiasm for design and construction. This role demands exceptional organizational skills, a consistent track record of high-performance, a passion for interdisciplinary projects, and an eagerness to contribute to Neuralink's mission!Key Responsibilities:As a senior mechanical engineer on our design team, you will be instrumental in conceptualizing and optimizing facilities. You will translate innovative concepts into detailed designs for HVAC, hydronic (chilled and heating water), plumbing, and process utility systems that seamlessly integrate with our facilities and manufacturing processes. Your work will encompass new construction as well as modifications to existing infrastructures. This position will support construction, facility operations, and various cross-functional departments to ensure that infrastructure systems are expertly designed to support all company activities.Develop conceptual designs and finalize designs for diverse project types including offices, laboratories, clean rooms, manufacturing facilities, warehouses, data centers, vivariums, and animal care facilities.Create high-quality Building Information Modeling (BIM) (REVIT) models, engineering drawings, and one-line diagrams for all mechanical, plumbing, and process systems.Design HVAC, hydronic, plumbing, and process utility systems that comply with codes, remain cost-effective, and satisfy quality and scheduling requirements.Prepare comprehensive construction drawing packages, including details, specifications, and operational sequences.Generate Building Automation System (BAS) and Direct Digital Control (DDC) control documents, scopes of work, and vendor quotes.Develop specifications, data sheets, and procurement requests for proposals (RFPs) for long-lead mechanical and plumbing equipment.Ensure all designs adhere to relevant codes and standards for optimal performance.

Join our innovative team as an ASIC Physical Design Engineer in the vibrant city of Austin, Texas. In this role, you will leverage your expertise to design and implement cutting-edge ASIC physical layouts, ensuring high performance and reliability.As a key member of our engineering department, you'll collaborate with cross-functional teams to drive projects from conception through to completion, all while adhering to strict timelines and quality standards.