Verification & Test Engineer - Robotics Software Team (Part-Time, Onsite)

Renesas Electronics Corporation seeks a Staff Design Verification Engineer based in Austin. This position helps maintain high standards during the design verification process, contributing to technology that appears in a wide range of electronic products. Role overview This role focuses on ensuring quality and reliability by verifying design implementations.…

wehrtyou is hiring a Design Verification Engineer to help ensure the quality and reliability of new designs. This position is available in Austin, Boulder, Chicago, London, or New York. Role overview This role centers on verifying the functionality of complex hardware or system designs. The Design Verification Engineer works closely with colleagues from different teams to review requirements, identify potential issues, and confirm that products meet high quality standards. What you will do Develop and maintain verification plans for new and existing designs Create and execute test cases to validate product functionality Collaborate with engineering and product teams to address issues and improve processes Location Positions are available in Austin, TX; Boulder, CO; Chicago, IL; London, UK; and New York, NY.

Join our dynamic team at Renesas Electronics as a Senior Staff Design Verification Engineer. In this pivotal role, you will leverage your expertise in design verification to ensure the highest quality of our semiconductor products. You will be responsible for developing and implementing verification strategies, collaborating with cross-functional teams, and driving innovation in our design processes.

Neuralink develops devices that connect directly with the human brain. The company’s technology focuses on restoring movement for people with paralysis, improving vision for those with impairments, and changing how people interact with digital systems. The Brain Interfaces Hardware Department leads the design of chip architecture and silicon systems for neural recording and stimulation. This group works on system-on-chip (SoC) solutions that support high-bandwidth brain-machine interfaces. Team members include engineers committed to advancing neurotechnology. Role overview The Physical Design and Verification Engineer manages the full physical design flow from RTL to GDSII. This includes: Synthesis Placement Clock tree synthesis Detailed routing Optimization Physical signoff verification Locations This position is based in Austin, Texas or Fremont, California.

About OLIXAt OLIX, we are at the forefront of revolutionizing the semiconductor industry. As AI technology rapidly evolves, the demand for advanced infrastructure grows, creating significant opportunities for innovation. Traditional hardware designs are becoming obsolete, and OLIX is leading the charge with our groundbreaking Optical Tensor Processing Unit (OTPU) that delivers unmatched performance and energy efficiency. Join us in shaping the future of AI hardware.The RoleWe are on the lookout for exceptional Senior/Staff Digital Verification Engineers who possess extensive expertise in CMOS digital design and verification. In this role, you will be responsible for ensuring the functional accuracy of high-speed, real-time data processing silicon—from initial algorithm modeling to verified RTL, sign-off, and silicon bring-up.As part of a dynamic, multidisciplinary team, you will contribute to the creation of innovative OTPUs where the digital, optical, and mixed-signal domains converge. We seek candidates who are passionate about developing high-performance systems that power the next generation of AI technology.Key ResponsibilitiesLead the comprehensive verification of high-throughput digital pipelines that support multi-GSPS input rates and continuous streaming data paths.Design and implement robust verification environments using SystemVerilog/UVM, focusing on constrained-random testing, coverage closure, and regression automation.Establish and execute assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance.Utilize formal verification methods (property checking, assertions, equivalence checking) to enhance simulation-based verification and expedite bug detection.Model and validate algorithms with MATLAB/Simulink or Python to ensure functional equivalence from algorithmic models to RTL and gate-level sign-off.Assist with FPGA prototyping and silicon bring-up by crafting targeted test cases, debugging strategies, and post-silicon validation plans.Collaborate effectively with digital design, optical hardware, mixed-signal, and software teams to guarantee seamless integration and performance.

About Etched Etched builds AI inference systems designed specifically for transformer models. The company’s technology delivers over ten times the performance of traditional solutions, while cutting both cost and latency. Etched’s advanced ASICs enable products that were once out of reach for GPUs, such as real-time video generation and complex reasoning agents. Backed by leading venture capital and a team of experienced engineers, Etched is focused on reshaping the infrastructure for one of the fastest-growing industries. Role Overview The Design Verification Engineer - Internal IP will join the Internal IP DV team in Austin. This role centers on validating custom IP blocks that drive Etched’s products, including systolic arrays, DMA engines, and NoCs. The work ensures these components are ready for silicon and deliver high performance. The position involves close collaboration with architects, RTL designers, and software, firmware, and emulation teams to confirm the integrity and efficiency of the hardware-software stack. What You Will Do Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems. Design and execute detailed verification plans covering functional correctness, edge cases, concurrency, and performance tuning. Debug complex datapath and protocol issues in RTL and testbench environments. Work directly with architects and designers to validate functionality and design intent. Partner with software, firmware, and emulation teams to support comprehensive bring-up and debugging. Help build reusable DV infrastructure, coverage models, and improve verification methodologies. Qualifications Expert knowledge of UVM and SystemVerilog. Strong analytical and debugging skills for complex digital designs. Solid understanding of computer architecture and core digital design concepts. Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics. Preferred Additional background with verification tools and methodologies is beneficial.

At Tenstorrent, we are at the forefront of AI technology, transforming performance benchmarks, usability, and cost-effectiveness in the industry. As AI reshapes the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. With a passionate team of technologists, we have engineered a high-performance RISC-V CPU from the ground up, driven by our enthusiasm for AI and our commitment to creating the premier AI platform. We prioritize collaboration, curiosity, and a relentless pursuit of challenging problems. Join us as we expand our team and welcome contributors of all experience levels.We are currently on the lookout for a SoC Physical Design Verification Engineer who will take charge of full-chip signoff and guarantee the manufacturability and high quality of silicon across advanced technology nodes. In this role, you'll spearhead physical verification closures (DRC, LVS, ERC, etc.), troubleshoot issues using standard industry PV tools, and work alongside RTL, PD, CAD, and packaging teams to ensure successful tapeouts. If you thrive in a dynamic environment and relish tackling intricate challenges in cutting-edge silicon, we want to hear from you.This position is hybrid, based in Santa Clara, CA; Austin, TX; or Fort Collins, CO.We invite applicants of various experience levels for this role. During the interview process, we will assess candidates for the appropriate level, and offers will be made accordingly, which may differ from the one in this posting.

About Etched Etched builds the first AI inference system tailored for transformers, delivering more than 10 times the performance of a B200 while cutting costs and latency. The company’s ASIC technology supports products that outpace traditional GPUs, making real-time video generation and advanced reasoning possible. Backed by hundreds of millions in funding and a team of experienced engineers, Etched is reshaping the infrastructure behind today’s fastest-growing industry. Role Overview The Design Verification Engineer - Interface IP will join the Interface IP DV team in Austin. This position works closely with architects, designers, and external vendors to ensure architectural requirements are met when developing IP subsystems and interfaces. The role involves validating correctness and performance across the hardware-software stack, requiring technical skill, creativity, and persistence to solve complex verification problems. What You Will Do Own one or more IP subsystems, such as PCIe, Ethernet, CPU (ARC/ARM), low power peripherals, and sensors. Interpret vendor IP configurations and coordinate with the internal IP team. Build and maintain verification environments using UVM and SystemVerilog to check functional correctness, performance, and compliance with IP specifications. Work with integration and SoC DV teams to ensure external IPs interact smoothly within the overall chip design. Drive coverage closure and sign-off by setting metrics, spotting gaps, and verifying edge cases and stress scenarios thoroughly.

Join Tenstorrent as a Full-Chip Physical Design Verification Engineer, where you will play a pivotal role in ensuring the integrity and performance of our cutting-edge semiconductor designs. You will collaborate closely with cross-functional teams to validate full-chip designs, enhancing their functionality, reliability, and efficiency.Your expertise will be crucial in developing and executing verification plans, identifying and resolving issues, and contributing to the advancement of our innovative technology. If you are driven by a passion for excellence and are eager to work in a dynamic environment, we want to hear from you!

Join Tenstorrent, a pioneer in advanced AI technology, where we are reshaping performance standards, user experience, and cost effectiveness in computing. As AI transforms the technological landscape, we are committed to integrating innovations across software models, compilers, platforms, networking, and semiconductors. Our talented team has built a high-performance RISC-V CPU from the ground up, driven by a collective enthusiasm for AI and an unwavering commitment to create the premier AI platform. We cherish collaboration, curiosity, and a shared mission to tackle challenging problems. We are expanding our team and invite applicants of all experience levels.The Staff Design for Test (DFT) Engineer will play a crucial role in developing high-performance designs for leading AI/ML architectures. This position involves comprehensive engagement in all aspects of implementation, from RTL to tapeout for various IP components on the chip. Key challenges include minimizing testing costs while achieving high coverage and facilitating debug and yield learning with minimal design interference. You will collaborate with a team of seasoned engineers across multiple ASIC domains.This position is hybrid, based in either Santa Clara, CA or Austin, TX.We encourage candidates with diverse experience levels to apply. During the interview process, candidates will be evaluated for the appropriate level, and compensation offers will be aligned accordingly.

Location: Austin, TX (Hybrid: 2 to 3 days onsite per week) Role overview The Senior Staff Systems Design Engineer at Weedmaps leads the transformation of the company’s design system into a scalable, production-ready foundation. This position connects Design, Engineering, and AI tooling, focusing on building, operationalizing, and scaling the system for all user interface surfaces. The role balances rapid development with high standards for usability and craftsmanship, ensuring alignment with engineering architecture and consistency across applications. Collaboration is central, working with Engineering (CI/CD, tokens, tooling), Creative (brand cohesion and evolution), and Product Design (development and iteration) to drive adoption and improve the product experience. What you will do Define and iterate on a multi-platform system for web and mobile, grounded in solid architecture, governance, and scalability principles. Own the system roadmap, setting priorities based on product needs, adoption gaps, and system performance. Collaborate with Design and Creative leaders to ensure quality craftsmanship, modern interaction patterns, and alignment with evolving brand standards. Design and implement core system components, including intuitive, flexible, and scalable APIs, variants, and composition patterns. Maintain high standards for visual accuracy, fidelity, accessibility (using React Aria), and interaction quality, including motion and state management. Continuously improve components based on real product usage and edge case scenarios. Implement automated quality systems such as visual regression testing, and conduct ongoing audits to uphold usability and craftsmanship, taking a cross-functional approach to quality. Lead migration of legacy user interfaces, ensuring smooth integration of key product surfaces (like CTAs and checkout flows) powered by the design system to increase adoption across the platform. Enhance Developer Experience by creating well-structured, intuitive component APIs that balance flexibility and simplicity. Establish a reliable tool-to-code pipeline (Figma, Claude, Builder, and others) to keep design artifacts and production components in sync and minimize drift. Partner with Engineering on architectural decisions (CI/CD, token systems, distribution infrastructure) and support enforcement mechanisms such as linting and token constraints to maintain system integrity. Introduce and standardize AI-assisted workflows, structure components for AI-friendly generation, and integrate tools (Builder.io, Gemini, and others) to improve consistency. Mentor designers and engineers, sharing best practices and guiding system usage to foster a strong, knowledgeable community.

At Tenstorrent, we are pioneering advancements in AI technology, setting new benchmarks for performance, usability, and cost-effectiveness. As AI transforms the computing landscape, our solutions are designed to integrate innovations across software models, compilers, platforms, networking, and semiconductors. Our talented team of technologists has built a high-performance RISC-V CPU from the ground up, driven by a shared enthusiasm for AI and a commitment to developing an exceptional AI platform. We prioritize collaboration, curiosity, and a dedication to tackling challenging problems. As we expand our team, we invite contributors of all experience levels to join us.We are looking for skilled Physical Design Engineers to develop high-performance blocks for our state-of-the-art CPU and AI/ML architectures. In this role, you'll manage the entire implementation process from synthesis to tapeout, collaborating with leading engineers to push the limits of performance, power, and area. If you are passionate about designing silicon that drives the future of AI computing and enjoy solving intricate design challenges, we would love to have you as part of our team.This position is hybrid, based in Austin, TX, Santa Clara, CA, or Fort Collins, CO.We welcome applicants with diverse experience levels. During the interview process, we will evaluate candidates to align offers with their respective skill levels, which may differ from the one stated in this posting.

Tenstorrent builds advanced AI hardware and software, with a focus on high-performance RISC-V CPUs. The team brings together specialists in software, compilers, platforms, networking, and semiconductors to tackle complex technical challenges. Collaboration and curiosity shape the company’s approach to product development. Role overview The Staff Engineer, CPU Core Verification leads verification at the CPU core level. This position plays a key part in defining the behavior of out-of-order RISC-V CPUs as they move from design to silicon. Location and work arrangement This is a hybrid role based in Austin, Texas. There is also an option to work from the Santa Clara, California office. Hiring process and leveling Tenstorrent reviews applicants with a range of backgrounds. During interviews, the team evaluates each candidate for the most suitable level. Final compensation aligns with the assessed level, which may differ from the one listed in this posting.

Join Renesas Electronics as a Senior Firmware Verification Engineer in Austin, Texas! In this pivotal role, you will be responsible for ensuring the quality and functionality of firmware products through rigorous testing and verification processes. You will collaborate with cross-functional teams to identify issues, develop test plans, and implement automation strategies to enhance product performance.

About BetterUp BetterUp’s mission centers on unlocking human potential. The company is rethinking the connection between employers and employees, focusing on meaningful work and personal growth. Every team member, from day one, receives support that goes beyond a paycheck: a dedicated BetterUp Coach, a personalized development plan, and a manager committed to growth. The culture values purpose-driven work and a supportive, collaborative atmosphere. Role Overview: Senior Staff Product Designer Location: Austin, TX This role shapes the future of BetterUp’s platform as the company moves from a suite of separate products to a unified, intelligent experience for users worldwide. The Senior Staff Product Designer is responsible for defining and evolving the design language and ensuring that products, tools, and experiences work together seamlessly. What You Will Do Envision and drive the integration of BetterUp’s products into a cohesive platform Balance user empathy with a structured, systems-oriented approach to design Collaborate closely with leaders in product, research, engineering, and design Define and uphold the principles that guide experience architecture Mentor senior designers and help maintain the quality and consistency of the design system Lead a small team of designers, influencing design quality and strategy across the company Team & Culture Design at BetterUp is central to the company’s mission of global human transformation. The environment is focused and fulfilling, best suited for those who are motivated by meaningful work and eager to make a lasting impact. Collaboration and mentorship are woven into daily work, and design has a seat at the table in shaping the company’s direction.

Location: Austin, TXEmployment Type: Full-time, In-OfficeDepartment: Engineering / ProductSalary: $160K – $200K annually + equity in the companyJoin our dynamic team as a Senior Staff Product Designer at Steadily, where we are dedicated to crafting intuitive and engaging experiences across the complete lifecycle of our customers. This full-time, in-office position is based in the vibrant city of Austin, TX.In your role, you will take charge of the entire design journey for critical product components. Your expertise will enable you to transform intricate requirements into sleek, high-performing interfaces. You will serve as the vital link between high-level vision and tangible code, ensuring that each user interaction is seamless and intuitive.Key Responsibilities:Lead the comprehensive design process from initial discovery through to delivery, rapidly iterating based on real user data and team insights.Craft user-centric experiences for our marketing site, web application, and documentation, aiding landlords in securing insurance for their rental properties.Work collaboratively with Product, Engineering, and Operations to transform real-world user needs into effective design solutions. Your designs will not just remain in Figma; they will be implemented swiftly, viewed by users, and will significantly impact product and business results.Produce wireframes, prototypes, and high-fidelity mockups that harmonize user objectives, technical constraints, and business goals. Conduct usability tests and gather feedback from a diverse user base, including landlords and insurance professionals, to validate design decisions and identify potential blind spots.Simplify intricate data and workflows such as coverage selection, policy document management, and production reporting into clear, digestible visuals.Review engineering pull requests to ensure designs are executed accurately and consistently. When discrepancies arise, you will effectively communicate solutions for rectification.Please note: this position may not be suitable for everyone. If you prefer a tranquil, pixel-perfect design role with slow timelines and minimal challenges, this may not be the right fit. However, if the above resonates with you, we would be thrilled to welcome you aboard.

Saronic Technologies is at the forefront of transforming maritime autonomy, committed to creating advanced solutions that significantly improve operational efficiency through innovative autonomous and intelligent platforms.Job OverviewWe are in search of a dedicated Systems Architecture, Integration, and Test Engineer (Test & Verification). In this crucial position, you will lead the verification, testing, and integration efforts for our state-of-the-art autonomous vessels. Your role will be essential in guaranteeing that our systems satisfy design specifications and performance standards through comprehensive verification and validation processes. You will design, plan, and implement testing campaigns at both subsystem and system levels, prioritizing reliability, safety, and integration efficacy. This entails defining test objectives and success metrics, equipping test articles, managing data collection and analysis, and conducting root cause investigations when discrepancies arise. You will collaborate closely with design engineers, test engineers, analysts, and operational teams to ensure that test outcomes inform design enhancements, thereby bolstering the reliability of each subsystem in our next-generation vessels. Your expertise will play a vital role in advancing the performance and dependability of our groundbreaking maritime technology as we forge ahead into the future of autonomous vessels.We understand that exceptional candidates may not always fulfill every requirement. We encourage individuals who are enthusiastic about our mission to apply, even if they do not meet all qualifications. Some of our most valued team members started their journeys this way. We appreciate innovators, problem-solvers, and quick learners, and we prioritize what you can contribute moving forward rather than solely your past experience. Your unique insights and experiences may be precisely what we need, so we welcome your application!ResponsibilitiesDevelop, own, and implement subsystem- and system-level verification and validation (V&V) plans to ensure designs meet functional, performance, autonomy, reliability, and safety requirements.Define test objectives, configurations, procedures, and success criteria for subsystem and full-system integration tests.Lead root cause analysis and failure investigations, implementing corrective actions for issues identified during R&D and qualification testing in collaboration with development, quality, and test teams.Analyze test results to uncover design flaws, system interactions, or performance gaps; effectively communicate findings and recommended actions.

Join our innovative team at Renesas Electronics as a Senior Staff Design Architecture Engineer. In this pivotal role, you will leverage your extensive expertise to drive the development of advanced design architectures that meet the evolving needs of our customers. Collaborate with cross-functional teams to design, implement, and optimize complex systems that enhance performance and efficiency.

About OLIXAt OLIX, we recognize that the demand for AI technology is accelerating at an unprecedented pace, leading to a significant infrastructure challenge. Current chip and power generation methods are insufficient to meet this demand. The industry is still reliant on outdated hardware designs, which are no longer effective. A transformative approach that enhances speed and efficiency represents the largest economic opportunity of the coming century. OLIX is pioneering this new paradigm with our Optical Tensor Processing Unit (OTPU), which delivers unmatched performance and energy efficiency that existing chips simply cannot achieve.Your RoleWe are in search of exceptional Senior/Staff Digital Design Engineers who specialize in CMOS digital design. You will take complete ownership of the design and implementation of high-speed, real-time data-processing silicon, from initial algorithm modeling through to verified RTL and silicon integration. Join a multidisciplinary team that is at the forefront of developing next-generation OTPUs, where digital, optical, and mixed-signal technologies converge. The ideal candidate will possess a robust background in electrical engineering and semiconductor physics, coupled with a fervor for creating reliable, high-performance digital circuits that propel AI hardware advancements.Key ResponsibilitiesArchitect, design, and implement high-throughput digital pipelines (multi-GSPS input rates, continuous streaming data paths, deep pipelining, and hand-shaking) utilizing advanced CMOS nodes.Quickly prototype and iterate in FPGA (Xilinx/AMD, Intel, or equivalents): develop real-time demonstrations, validate high-speed transceivers, and integrate feedback into ASIC designs.Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence up to gate-level sign-off.Lead RTL development (SystemVerilog / Verilog / VHDL), encompassing synthesis, static-timing closure, and both formal and constrained-random verification.Evaluate power, performance, and area (PPA), employing innovative strategies to meet aggressive bandwidth-per-watt objectives.Collaborate with optical hardware, mixed-signal, and software teams to optimize data-converter interfaces, clock-domain crossings, and firmware abstractions.Mentor junior engineers, facilitate design reviews, and promote best-practice design methodologies.Qualifications & Experience7+ years of direct experience in digital design for high-performance applications.Strong proficiency in CMOS design methodologies and digital circuit development.Extensive experience with FPGA prototyping and algorithm validation.Expertise in RTL design languages (SystemVerilog / Verilog / VHDL) and verification processes.Familiarity with power, performance, and area trade-offs in digital design.Excellent collaborative and communication skills for cross-functional teamwork.Demonstrated ability to lead and mentor engineering teams.