About the job
Join d-Matrix, where we are dedicated to leveraging the power of generative AI to revolutionize technology. We are pioneering in both software and hardware innovation, constantly expanding the limits of what is achievable. Our workplace culture emphasizes respect and collaboration.
We greatly value humility and encourage open communication. Our team is diverse and inclusive, where varied perspectives contribute to superior solutions. We seek individuals who are passionate about overcoming challenges and are motivated by results. Are you ready to discover your potential? Together, we can explore the vast possibilities of AI.
Location:
This position is hybrid, requiring onsite work at our headquarters in Santa Clara, CA for three days each week.
Role Overview: Senior Staff Design Verification Engineer
Key Responsibilities:
We aim to build a company culture that withstands the tests of time. This role presents a unique opportunity for you to express your creativity and emerge as a leader in an industry poised to make a global impact. We are committed to fostering a culture of transparency, inclusiveness, and intellectual honesty, ensuring that all team members continuously learn and enjoy the journey. You will work on pioneering our industry’s first highly programmable in-memory computing architecture, applicable across a wide range of applications from cloud to edge. Collaborate with a highly experienced team dedicated to building a successful business.
Qualifications:
Minimum qualifications include:
A Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience, or a Master's degree in Electrical Engineering, Computer Science, or a related field with 7+ years of experience.
Proven experience throughout the SoC verification cycle from architecture to tape-out and bring-up.
Strong understanding of verification methodologies such as UVM/OVM.
Hands-on experience with ASIC-SoC design verification testing and debugging.
Proficiency in SystemVerilog randomization constraints, coverage, and assertion methodologies.
Excellent problem-solving skills and a fervent enthusiasm for tackling challenges, particularly within the AI domain.
Extensive experience with SystemVerilog and verification methodologies (UVM/OVM/VMM).
